An operand storage compare (osc) detecting device using column and row signals in a buffer storage

Claim 2

An operand store compare (OSC) detecting device in a buffer controller, comprising: a buffer storage accessed by columns and rows; a read-out buffer address array responsive to first real address representing read-out operand data of a first instruction for transforming the first real address into a first pair including a column address and a row address and for outputting said first pair to said buffer storage; a write-in buffer address array responsive to a second real address representing write-in operand data of a second instruction for transforming said second real address into a second pair including a column address and a row address and for outputting said second pair to said buffer storage; and an OSC detecting section connected with said read-out buffer address array and said write-in buffer address array for comparing said first pair of a column address and a row address with said second pair of a column address and a row address to output a detection signal when both the pairs coincide with each other.

Claim 3

An OSC detecting device according to claim 1, wherein said first pair of a column address and a row address represents the starting address of said read-out operand data in said buffer storage and said second pair of a column address and a row address represents the starting address of said write-in operand data in said buffer storage.

Claim 4

An OSC detecting device according to claim 2, wherein said OSC detecting section includes: first comparing means for comparing said first row address with said second row address; second comparing means for comparing said first and said second column addresses, and a signal representing the length of said read-out operand data and a signal representing the length of said write-in operand data to determine whether said read-out operand data and said write-in operand data are superposed on each other or not; and a logic circuit connected with said first and said second comparing means, and receiving a read-out request signal for said read-out operand data and a write-in request signal for said write-in operand data, signals representing whether said first and said second real addresses have hit their respective buffer address arrays or not, and comparison outputs from said first and said second comparing means, for effecting logical calculations to output said OSC detection signal.

Claim 5

An OSC detecting device according to claim 1, wherein said second instruction is a succeeding instruction of said first instruction.

Claim 6

An OSC detecting device according to claim 1, wherein the content of said read-out buffer address array and the content of said write-in buffer address array are coincident with each other.

Claim 7

An operand store compare (OSC) detecting device in a buffer controller, comprising: a buffer storage constituted by columns and rows; first register means for holding a first address representative of read-out operand data of a first instruction; second register means for holding a second address representative of write-in operand data of a second instruction; first means connected between said first register means and said buffer storage and responsive to said first address, for outputting a first pair of a column signal and a row signal indicating the column and row of said read-out operand data stored in said buffer storage; second means connected between said second register means and said buffer storage and responsive to said second address, for outputting a second pair of a column signal and a row signal indicating the column and row of said write-in operand data stored in said buffer storage; and an OSC detecting section connected to said first and second means for comparing said first and second pairs to output a detection signal for inhibiting a read-out operation of said first instruction before a write-in operation of said second instruction, when both the pairs coincide with each other.

Claim 8

An operand store compare (OSC) detecting device in a buffer controller, comprising: a buffer storage constituted by columns and rows; first register means for holding a first address representative of read-out operand data of a first instruction; second register means for holding a second address representative of write-in operand data of a second instruction; first means connected between said first register means and said buffer storage and responsive to said first address, for outputting a first pair of a column signal and a row signal indicating the column and row of said read-out operand data stored in said buffer storage; second means connected between said second register means and said buffer storage and responsive to said second address, for outputting a second pair of a column signal and a row signal indicating the column and row of said write-in operand data stored in said buffer storage; and an OSC detecting section connected to said first and second means for comparing said first and second pairs to output a detection signal for inhibiting a read-out operation of said first instruction before a write-in operation of said second instruction, when both the pairs coincide with each other.

Claim 9

An OSC detecting device according to claim 6, wherein said first means includes: a read-out address transforming buffer for transforming the first address held in said first register means into a first real address; and a read-out buffer address array responsive to said first real address, for detecting a column and a row of data in said buffer storage corresponding to said read-out operand data; and said second means includes: a write-in address transforming buffer for transforming the second address held in said second register means into a second real address; and a write-in buffer address array responsive to said second real address, for detecting a column and a row of data in said buffer storage corresponding to said write-in operand data.