US5099151A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Buffer circuit for logic level conversion
Assignee: Fujitsu Ltd
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Filing: 1991-03-14
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Granted: 1992-03-24
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Expires: 2011-03-14
Abstract
Abstract A semiconductor interface circuit comprises a threshold circuit supplied with an input logic signal and an internal reference signal for discriminating the logic level thereof, and a reference circuit supplied with an external reference voltage for producing the internal reference signal. The threshold circuit comprises a first load, a first enhancement mode FET and a second load connected in series between a first power terminal and a second power terminal, wherein the internal reference signal is supplied to the gate of the first enhancement mode FET. Further, a first FET having a gate to which the input logic signal is supplied, is provided between the first and second power supply terminals. The first FET produces the output at the drain thereof. The reference circuit comprises a third load, a second enhancement mode FET and a fourth load connected in series between the first and second power terminals, wherein the drain and the gate are connected. Further, a second FET is provided across the first and second power terminals. The second FET is supplied with the reference voltage at a gate thereof, and the internal reference voltage is obtained at the drain of the second enhancement mode FET.
Inventors
- 👤 Yuu Watanabe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 15:26
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/0175; H03K19/0185; H03K19/018507; H03K19/018535; H03K19/018542
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
428 words
A semiconductor interface circuit supplied with an input logic signal having either a first logic level or a second, different logic level, for producing an output logic signal in correspondence to the logic level of the input signal, comprising: a threshold circuit supplied with the input logic signal and an internal reference signal for discriminating the logic level thereof based upon a comparison of the logic level of the input logic signal and the internal reference signal and producing the output logic signal in response to the result of comparison; a reference circuit supplied with an external reference voltage for producing the internal reference signal; a first power supply terminal for receiving a first power voltage; and a second power supply terminal for receiving a second power voltage that is lower than the first power voltage; said threshold circuit comprising first load means having a first end connected to the first power supply terminal and a second end, a first enhancement mode field effect transistor having a drain connected to the second end of the first load means, a gate connected to the reference circuit for receiving the internal reference signal and a source, second load means having a first end connected to the source of the first enhancement mode field effect transistor and a second end connected to the second power supply terminal, and a first field effect transistor having a gate supplied with the input logic signal, a drain connected to the first power supply terminal and a source connected to the second power supply terminal, said threshold circuit producing the output logic signal at the drain of the enhancement mode field effect transistor; said reference circuit comprising third load means having a first end connected to the first power supply terminal and a second end, a second enhancement mode field effect transistor having a drain connected to the second end of the third load means, a gate connected to the drain of the second enhancement mode field effect transistor and further to the gate of the first enhancement mode field effect transistor and a source, said second enhancement mode field effect transistor producing the internal reference signal at the drain thereof, fourth load means having a first end connected to the source of the second enhancement mode field effect transistor and a second end connected to the second power supply terminal, and a second field effect transistor having a gate supplied with the external reference voltage, a drain connected to the first power supply terminal and a source connected to the second power supply terminal.
Claim 2
Dependent Claim
428 words
A semiconductor interface circuit supplied with an input logic signal having either a first logic level or a second, different logic level, for producing an output logic signal in correspondence to the logic level of the input signal, comprising: a threshold circuit supplied with the input logic signal and an internal reference signal for discriminating the logic level thereof based upon a comparison of the logic level of the input logic signal and the internal reference signal and producing the output logic signal in response to the result of comparison; a reference circuit supplied with an external reference voltage for producing the internal reference signal; a first power supply terminal for receiving a first power voltage; and a second power supply terminal for receiving a second power voltage that is lower than the first power voltage; said threshold circuit comprising first load means having a first end connected to the first power supply terminal and a second end, a first enhancement mode field effect transistor having a drain connected to the second end of the first load means, a gate connected to the reference circuit for receiving the internal reference signal and a source, second load means having a first end connected to the source of the first enhancement mode field effect transistor and a second end connected to the second power supply terminal, and a first field effect transistor having a gate supplied with the input logic signal, a drain connected to the first power supply terminal and a source connected to the second power supply terminal, said threshold circuit producing the output logic signal at the drain of the enhancement mode field effect transistor; said reference circuit comprising third load means having a first end connected to the first power supply terminal and a second end, a second enhancement mode field effect transistor having a drain connected to the second end of the third load means, a gate connected to the drain of the second enhancement mode field effect transistor and further to the gate of the first enhancement mode field effect transistor and a source, said second enhancement mode field effect transistor producing the internal reference signal at the drain thereof, fourth load means having a first end connected to the source of the second enhancement mode field effect transistor and a second end connected to the second power supply terminal, and a second field effect transistor having a gate supplied with the external reference voltage, a drain connected to the first power supply terminal and a source connected to the second power supply terminal.
Claim 3
Dependent Claim
47 words
A semiconductor circuit as claimed in claim 1 in which said first enhancement mode field effect transistor has a characteristic substantially identical with the second enhancement mode field effect transistor, and said first field effect transistor has a characteristic substantially identical with the second field effect transistor.
Claim 4
Dependent Claim
59 words
A semiconductor circuit as claimed in claim 1 in which said reference circuit and said threshold circuit are formed on a same semiconductor chip with substantially symmetric relationship such that said reference circuit forms a mirror image of the threshold circuit, except for the interconnection of the drain and the gate of the second enhancement mode field effect transistor.
Claim 5
Dependent Claim
67 words
A semiconductor circuit as claimed in claim 3 in which said first enhancement mode field effect transistor has a gate length and a gate width that are identical with those of the second enhancement mode field effect transistor of the reference circuit, and said first field effect transistor has a gate length and a gate width that are identical with those of the second field effect transistor.
Claim 6
Dependent Claim
332 words
A semiconductor circuit as claimed in claim 1 in which said first load means comprises a first depletion mode field effect transistor having a drain in correspondence to the first end of the first load means connected to the first power supply terminal and a source in correspondence to the second, opposing end connected to the drain of the first enhancement mode field effect transistor, said first depletion mode field effect transistor having a gate connected to the source thereof to form a constant current source, said second load means comprises a second depletion mode field effect transistor having a drain in correspondence to the first end of the second load means connected to the source of the first enhancement mode field effect transistor and a source in correspondence to the second, opposing end connected to the second power supply terminal, said second depletion mode field effect transistor having a gate connected to the source thereof to form a constant current source, said third load means comprises a third depletion source, said third load means comprises a third depletion mode field effect transistor having a drain in correspondence to the first end of the third load means that is connected to the first power supply terminal and a source in correspondence to the second, opposing end connected to the drain of the second enhancement mode field effect transistor, said third depletion mode field effect transistor having a gate connected to the source thereof to form a constant current source, and said fourth load resistance means comprises a fourth depletion mode field effect transistor having a drain in correspondence to the first end of the fourth load means connected to the source of the second enhancement mode field effect transistor and a source in correspondence to the second, opposing end of the fourth load means connected to the second power supply terminal, said fourth depletion mode field effect transistor having a gate connected to the source thereof to form a constant current source.
Claim 7
Dependent Claim
333 words
A semiconductor circuit as claimed in claim 5 in which said first load means comprises a first depletion mode field effect transistor having a drain in correspondence to the first end of the first load means connected to the first power supply terminal and a source in correspondence to the second, opposing end connected to the drain of the first enhancement mode field effect transistor, said first depletion mode field effect transistor having a gate connected commonly to the gate of the field effect transistor for receiving the input logic signal, said second load means comprises a second depletion mode field effect transistor having a drain in correspondence to the first end of the second load means connected to the source of the first enhancement mode field effect transistor and a source in correspondence to the second, opposing end connected to the second power supply terminal, said second depletion mode field effect transistor having a gate connected to the source thereof to form a constant current source, said third load means comprises a third depletion mode field effect transistor having a drain in correspondence to the first end of the third load means that is connected to the first power supply terminal and a source in correspondence to the second, opposing end connected to the drain of the second enhancement mode field effect transistor, said third depletion mode field effect transistor having a gate connected commonly to the gate of the second field effect transistor for receiving the reference voltage, and said fourth load resistance means comprises a fourth depletion mode field effect transistor having a drain in correspondence to the first end of the fourth load means connected to the source of the second enhancement mode field effect transistor and a source in correspondence to the second, opposing end of the fourth load means connected to the second power supply terminal, said fourth depletion mode field effect transistor having a gate connected to the source thereof to form a constant current source.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-03-24 | 1995-09-23 | 1996-03-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-03-24 | 1999-09-23 | 2000-03-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-03-24 | 2003-09-23 | 2004-03-24 | $7700.00 | Window Closed / Lapsed |