Pipelined decision feedback decoder

Claim 2

A decoder for providing decisions determing sample values of a digital data stream transmitted through a channel, comprising: means for providing magnitude comparison having a first input for receiving sequentially said sample values corresponding to data transmitted through said channel, and a second input for receiving an adjustable threshold for comparing each sample value to said threshold, said means providing decisions determing each of said sample values as having a first signal value when said sample value exceeds said threshold, and a second signal value when said sample value is equal to or below said threshold; means for storing a predetermined number of decisions provided by said means for providing magnitude comparison; first and second threshold adjustment circuits each receiving said predetermined number of stored decisions and in response thereto providing a respective adjusted threshold value, said first threshold adjustment circuit providing said adjusted threshold value based on a first predetermined signal value assigned to a next decision in sequence, following said stored decisions, and said second threshold adjustment circuit providing said adjusted threshold value based on a second predetermined signal value assigned to said next decision in sequence, following said stored decisions; and switch means having a selection input for receiving an actual value of said next decision from said means for providing magnitude comparison, and in response thereto applying to said second input of said means for providing magnitude comparison that one of said adjusted threshold values which is based on said actual value of said next decision.

Claim 3

The decoder of claim 1 wherein: said received sequential sample values have digital values, each said decision provided by said means for magnitude comparison is equal to a first logic level when said digital sample value exceeds said threshold, and each said decision is equal to a second logic level when said digital sample value is equal to or below said threshold; said first and second threshold adjustment circuits are respective logic circuits; and wherein said first logic circuit provides said adjusted threshold value based on a first logic level assigned to a next decision in sequence, following said stored decisions, and said second logic circuit provides said adjusted threshold value based on a second logic level assigned to said next decision in sequence, following said stored decisions.

Claim 4

A decoder for providing decisions determining bit values of a digital data stream transmitted through a channel, comprising: means for providing magnitude comparison having a first input for receiving sequential digital values corresponding to data bits of said data stream transmitted through said channel, and a second input for receiving an adjustable threshold for comparing each said digital value to said threshold, said means providing decisions determining the value of each said data bit as having a first logic level when said digital value exceeds said threshold, and a second logic level when said digital value is equal to or below said threshold; means for storing a predetermined number of decisions provided by said means for providing magnitude comparison; first and second logic circuits, each receiving said predetermined number of stored decisions and in response thereto providing a respective adjusted threshold value, said first logic circuit providing said adjusted threshold value based on a first logic level assigned to a next decision in sequence, following said stored decisions, and said second logic circuit providing said adjusted threshold value based on a second logic level assigned to said next decision in sequence, following said stored decisions; and switch means having a selection input for receiving an actual value of said next decision from said means for providing magnitude comparison, and in response thereto applying to said second input of said means for providing magnitude comparison that one of said adjusted threshold values which is based on said actual value of said next decision.

Claim 5

A decoder for providing decisions determining bit values of a digital data stream transmitted through a channel, comprising: means for providing magnitude comparison having a first input for receiving sequential digital values corresponding to data bits of said data stream transmitted through said channel, and a second input for receiving an adjustable threshold for comparing each said digital value to said threshold, said means providing decisions determining the value of each said data bit as having a first logic level when said digital value exceeds said threshold, and a second logic level when said digital value is equal to or below said threshold; means for storing a predetermined number of decisions provided by said means for providing magnitude comparison; first and second logic circuits, each receiving said predetermined number of stored decisions and in response thereto providing a respective adjusted threshold value, said first logic circuit providing said adjusted threshold value based on a first logic level assigned to a next decision in sequence, following said stored decisions, and said second logic circuit providing said adjusted threshold value based on a second logic level assigned to said next decision in sequence, following said stored decisions; and switch means having a selection input for receiving an actual value of said next decision from said means for providing magnitude comparison, and in response thereto applying to said second input of said means for providing magnitude comparison that one of said adjusted threshold values which is based on said actual value of said next decision.

Claim 6

The decoder of claim 3 wherein said means for storing is a shift register means having a predetermined number of series connected storage elements for delaying said decisions for one clock cycle, each storage element having an output for applying said delayed decision therefrom, and wherein said output of a first said series connected storage element is coupled to said selection input of said switch means and said outputs of a second and subsequent series connected storage elements are coupled to said first and second logic circuit, respectively.

Claim 7

The decoder of claim 3 wherein said means for providing magnitude comparison comprises adder means for providing a sum of a digital value received at its first input and of an adjusted threshold value received at its second input, and wherein said decision is equal to said first logic level when said sum is greater than zero, and to said second logic level when said sum is equal to or less than zero.

Claim 8

The decoder of claim 3 wherein the first and second logic means comprise random access memory means.

Claim 9

A decoder for providing decisions determining bit values of a digital data stream transmitted through a channel, comprising: means for providing magnitude comparison having a first input for receiving sequentially digital sample values corresponding to data bits of said transmitted data stream at a predetermined clock frequency, and a second input for receiving an adjustable threshold, said magnitude comparison means comparing each said digital sample value to said threshold, and providing subsequent decisions determining the value of each said data bit as having a first logic level when said digital sample value exceeds said threshold, and a second logic level when said digital sample value is equal to or below said threshold; shift register means for storing a predetermined number of consecutive decisions provided by said means for providing magnitude comparison, said shift register means having a predetermined number of series connected storage elements for delaying said consecutive decisions for one clock cycle; first and second logic circuits, each receiving said predetermined number of stored decisions and in response thereto providing simultaneously a respective adjusted threshold value, said first logic circuit providing said adjusted threshold value based on a first logic level assigned to a next decision in sequence, following said stored decisions, and said second logic circuit providing said adjusted threshold value based on a second logic level assigned to said next decision in sequence following said stored decisions; and switch means having a selection input for receiving an actual value of said next decision from said means for providing magnitude comparison, and in response thereto applying to said second input of said means for providing magnitude comparison that one of said adjusted threshold values which is based on said actual value of said next decision; and wherein each said storage element of said shift register means has an output for applying a delayed decision therefrom, said output of a first said series connected storage element is coupled to said selection input of said switch means and said outputs of all storage elements are coupled to said first and second logic circuits, respectively.

Claim 10

A decoder for providing decisions determining bit values of a digital data stream transmitted through a channel, comprising: means for providing magnitude comparison having a first input for receiving sequentially digital sample values corresponding to data bits of said transmitted data stream at a predetermined clock frequency, and a second input for receiving an adjustable threshold, said magnitude comparison means comparing each said digital sample value to said threshold, and providing subsequent decisions determining the value of each said data bit as having a first logic level when said digital sample value exceeds said threshold, and a second logic level when said digital sample value is equal to or below said threshold; shift register means for storing a predetermined number of consecutive decisions provided by said means for providing magnitude comparison, said shift register means having a predetermined number of series connected storage elements for delaying said consecutive decisions for one clock cycle; first and second logic circuits, each receiving said predetermined number of stored decisions and in response thereto providing simultaneously a respective adjusted threshold value, said first logic circuit providing said adjusted threshold value based on a first logic level assigned to a next decision in sequence, following said stored decisions, and said second logic circuit providing said adjusted threshold value based on a second logic level assigned to said next decision in sequence following said stored decisions; and switch means having a selection input for receiving an actual value of said next decision from said means for providing magnitude comparison, and in response thereto applying to said second input of said means for providing magnitude comparison that one of said adjusted threshold values which is based on said actual value of said next decision; and wherein each said storage element of said shift register means has an output for applying a delayed decision therefrom, said output of a first said series connected storage element is coupled to said selection input of said switch means and said outputs of all storage elements are coupled to said first and second logic circuits, respectively.