US5097208A
Expired / Lapsed
US
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Apparatus and method for measuring gate delays in integrated circuit wafers
Assignee: Altera Corp
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Filing: 1990-12-05
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Granted: 1992-03-17
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Expires: 2010-12-05
Abstract
Abstract Apparatus and a method for measuring average individual gate delays on integrated circuit wafers without the need for high bandwidth is provided. A chain of gates is provided on the wafer. A reference signal is propagated through the chain to produce a delayed signal. The delayed signal is logically combined with the reference signal to provide a periodic train of pulses whose period is proportional to that of the reference signal. The pulse widths represent the total gate delay of the chain, and are determined by statistically sampling the pulse train to determine its duty cycle. The apparatus and method are compatible with automated testing equipment and methods which can be synchronized with the reference signal.
Inventors
- 👤 David Chiang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 03:11
CPC Classifications
G; G01; G01R; G01R29/00; G01R29/02; G01R29/027; G01R29/0273
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
228 words
Apparatus for measuring gate delays in an integrated circuit wafer, said apparatus comprising: a chain of logical elements on said wafer, said chain comprising a number of said logical elements connected in cascade fashion, each of said logical elements having an elemental input and an elemental output, the elemental input of a first logical element in said chain being a chain input and the elemental output of a last logical element in said chain being a chain output, each of said logical elements having an elemental gate delay, and said chain having a total gate delay; means for generating a reference clock signal having a reference period longer than twice said total gate delay; means for applying said reference clock signal to said chain input; gate means having a first gate input, a second gate input and a gate output, said chain output being applied to said first gate input, said reference clock signal being applied also to said second gate input, such that said gate output is a train of periodic pulses having a pulse width proportional to said total gate delay and a period proportional to said reference period; means for repeatedly sampling said gate output to determine a duty cycle of said gate output; and means for calculating said elemental gate delay from said number, said pulse width, said reference period, and said duty cycle.
Claim 2
Dependent Claim
228 words
Apparatus for measuring gate delays in an integrated circuit wafer, said apparatus comprising: a chain of logical elements on said wafer, said chain comprising a number of said logical elements connected in cascade fashion, each of said logical elements having an elemental input and an elemental output, the elemental input of a first logical element in said chain being a chain input and the elemental output of a last logical element in said chain being a chain output, each of said logical elements having an elemental gate delay, and said chain having a total gate delay; means for generating a reference clock signal having a reference period longer than twice said total gate delay; means for applying said reference clock signal to said chain input; gate means having a first gate input, a second gate input and a gate output, said chain output being applied to said first gate input, said reference clock signal being applied also to said second gate input, such that said gate output is a train of periodic pulses having a pulse width proportional to said total gate delay and a period proportional to said reference period; means for repeatedly sampling said gate output to determine a duty cycle of said gate output; and means for calculating said elemental gate delay from said number, said pulse width, said reference period, and said duty cycle.
Claim 3
Dependent Claim
16 words
The apparatus of claim 1 wherein said logical elements are inverters and said number is even.
Claim 4
Dependent Claim
40 words
The apparatus of claim 1 wherein said logical elements are AND gates, each of said AND gates having two effective inputs, one of said effective inputs being held high, and the other of said effective inputs being said elemental input.
Claim 5
Dependent Claim
13 words
The apparatus of claim 1 wherein said gate means is an XOR gate.
Claim 6
Dependent Claim
26 words
The apparatus of claim 1 wherein said means for repeatedly sampling said gate output samples said gate output at regular intervals separated by a sampling period.
Claim 7
Dependent Claim
17 words
The apparatus of claim 5 wherein said sampling period is greater than one half said reference period.
Claim 8
Dependent Claim
21 words
The apparatus of claim 1 wherein said means for repeatedly sampling said gate output samples said gate output at random intervals.
Claim 9
Dependent Claim
75 words
The apparatus of claim 1 wherein said means for sampling said gate output comprises: a D-type flip-flop having a D input, a clock input and a Q output; means for generating a sampling clock signal; and means for applying said sampling clock signal to said flip-flop clock input; wherein: said chain output is connected to said D input; and said Q output reflects said chain output on each rising edge of said sampling clock signal.
Claim 10
Dependent Claim
91 words
The apparatus of claim 8 wherein said means for sampling said gate output further comprises: first and second counter means; means for determining when said Q output and said clock input are high simultaneously and for incrementing said first counter means when said Q output and said flip-flop clock input are simultaneously high; means for incrementing said second counter means when said flip-flop clock input is high; and means for dividing the contents of said first counter means by the contents of said second counter means to determine said duty cycle.
Claim 11
Dependent Claim
49 words
The apparatus of claim 9 wherein said means for determining when said Q output and said clock input are simultaneously high comprises an enable input on said first counter means connected to said Q output and a clock input on said first counter means connected to said sampling clock.
Claim 12
Dependent Claim
40 words
The apparatus of claim 1 wherein said means for calculating said elemental gate delay calculates said elemental gate delay by determining a product of one-half said reference period and said duty cycle and dividing said product by twice said number.
Claim 13
Independent Claim
131 words
A method for measuring gate delays in an integrated circuit wafer, said method comprising the steps of: generating a delayed signal by inputting a reference signal having a reference period into a chain of a known number of gates on said wafer, each gate in said chain having an elemental gate delay and said chain having a total gate delay; logically combining said delayed signal with said reference signal to produce a combined signal in the form of a train of periodic pulses having a pulse width proportional to said total gate delay and a period proportional to said reference period; repeatedly sampling said combined signal to determine a duty cycle thereof; and calculating said elemental gate delay from said member, said pulse width, said reference period, and said duty cycle.
Claim 14
Independent Claim
131 words
A method for measuring gate delays in an integrated circuit wafer, said method comprising the steps of: generating a delayed signal by inputting a reference signal having a reference period into a chain of a known number of gates on said wafer, each gate in said chain having an elemental gate delay and said chain having a total gate delay; logically combining said delayed signal with said reference signal to produce a combined signal in the form of a train of periodic pulses having a pulse width proportional to said total gate delay and a period proportional to said reference period; repeatedly sampling said combined signal to determine a duty cycle thereof; and calculating said elemental gate delay from said member, said pulse width, said reference period, and said duty cycle.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-03-17 | 1995-09-16 | 1996-03-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-03-17 | 1999-09-16 | 2000-03-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-03-17 | 2003-09-16 | 2004-03-17 | $7700.00 | Window Closed / Lapsed |