US3681693A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Measurement of maximum dynamic skew in parallel channels
Assignee: RCA Corp
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Filing: 1970-11-27
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Granted: 1972-08-01
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Expires: 1990-11-27
Abstract
Abstract Circuit for determining the times the first and last signals representing bits of character are read from a tape or other recording medium. Signals representing the bits are applied to the inputs of both an OR gate and a parity checker. The parity checker produces an output signal whenever the signals at its input comprise, for example, an odd number. Because of skew, the parity checker may produce several pulses of short duration before it stabilizes. The parity checker is coupled to a circuit that produces an output signal only in response to an input signal having greater than a given duration. The skew is measured by comparing the output signal of the circuit with the output signal of the OR gate delayed for a time period equal to the given duration.
Inventors
- 👤 Chia Ying Hsueh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 09:56
CPC Classifications
G; G06; G06K; G06K7/00; G06K7/01; G06K7/016
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
177 words
A circuit for measuring the skew between the first and the last arriving signals of a group of signals intended to be in time coincidence comprising, in combination: a plurality of signal lines each for carrying one signal of said group of signals; first circuit means coupled to all of said signal lines and receptive of all of said signals for producing an output signal in response to the first occurring one of said signals; second circuit means coupled to all of said signal lines and receptive of all of said signals for producing a plurality of output signals during the period between the first and the last arriving signal, the last such output signal occurring in response to the last arriving of said signals; means coupled to said second circuit means for producing an output signal only in response to said last such output signal; and means coupled to said last-named means and to said first circuit means for measuring the interval of time between said first and last arriving signals of said group of signals.
Claim 2
Dependent Claim
177 words
A circuit for measuring the skew between the first and the last arriving signals of a group of signals intended to be in time coincidence comprising, in combination: a plurality of signal lines each for carrying one signal of said group of signals; first circuit means coupled to all of said signal lines and receptive of all of said signals for producing an output signal in response to the first occurring one of said signals; second circuit means coupled to all of said signal lines and receptive of all of said signals for producing a plurality of output signals during the period between the first and the last arriving signal, the last such output signal occurring in response to the last arriving of said signals; means coupled to said second circuit means for producing an output signal only in response to said last such output signal; and means coupled to said last-named means and to said first circuit means for measuring the interval of time between said first and last arriving signals of said group of signals.
Claim 3
Dependent Claim
26 words
A circuit as set forth in claim 1 wherein said first circuit means comprises an OR gate and said second circuit means comprises a parity checker.
Claim 4
Dependent Claim
47 words
A circuit as set forth in claim 1 wherein said means for producing an output signal only in response to said last output signal comprises a circuit for producing an output pulse only in response to an input pulse of duration greater than said interval of time.
Claim 5
Dependent Claim
67 words
A circuit as set forth in claim 3 wherein said last-named means of claim 1 includes delay means coupled to said first circuit means for producing an output signal an interval of time after the receipt of the first occurring signal of said group of signals and comprises a counter responsive to said delayed output signal and to the delayed signal produced by said second output means.
Claim 6
Dependent Claim
43 words
A circuit as set forth in claim 4 further including coincidence gating means responsive to the signal from the delay means and an output signal from the second circuit means for producing an output signal indicative of skew exceeding said interval of time.
References Cited (Backward Citations)
US2951985A
Cited
US3414816A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-08-01 | 1976-01-31 | 1976-08-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-08-01 | 1980-01-31 | 1980-08-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-08-01 | 1984-01-31 | 1984-08-01 | $7700.00 | Window Closed / Lapsed |