US5097151A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Sequential finite-state machine circuit and integrated circuit
Assignee: US Philips Corp
•
Filing: 1991-02-13
•
Granted: 1992-03-17
•
Expires: 2011-02-13
Abstract
Abstract Additional logic is added to a sequential finite-state machine circuit having a self-initialing behavior so that the circuit can be simulated. From any state, a rest state is reached by way of a given sequence of values of an input signal. Transitions between states of the finite-state machine are realized by the additional logic, such that the simulated circuit realizes the transition from an unknown state to a known, absorbing state in steps.
Inventors
- 👤 Lars A. R. Eerenstein
- 👤 Mathias N. M. Muris
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 06:14
CPC Classifications
G; G05; G05B; G05B19/00; G05B19/02; G05B19/04; G05B19/045
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
183 words
A sequential finite state machine circuit, comprising a set of N bistable elements {FF(1), . . . , FF(N)} and a set of combinatory logic connected thereto, the combination of logic values of the bistable elements defining a state of the circuit which is a representation of a state of a finite state machine, the circuit changing over to a next state at instants which are determined by a clock signal under the influence of the combinatory logic, the current state of the circuit, and an input signal, the set of combinatory logic realizing transitions between states of the finite-state machine in the circuit, characterized in that from any state a rest state is reached by way of a given sequence of X values of the input signal, {c(0), c(1), . . . , c(X-1)}, starting with c(0) every sub-sequence {c(0), c(1), . . . , c(J-1)}, having the length J, occurring in the given sequence of X values of the input signal, where 1<=J<=X, or a sub-sequence having the length J which is a one-to-one representation thereof being stored in the circuit.
Claim 2
Dependent Claim
183 words
A sequential finite state machine circuit, comprising a set of N bistable elements {FF(1), . . . , FF(N)} and a set of combinatory logic connected thereto, the combination of logic values of the bistable elements defining a state of the circuit which is a representation of a state of a finite state machine, the circuit changing over to a next state at instants which are determined by a clock signal under the influence of the combinatory logic, the current state of the circuit, and an input signal, the set of combinatory logic realizing transitions between states of the finite-state machine in the circuit, characterized in that from any state a rest state is reached by way of a given sequence of X values of the input signal, {c(0), c(1), . . . , c(X-1)}, starting with c(0) every sub-sequence {c(0), c(1), . . . , c(J-1)}, having the length J, occurring in the given sequence of X values of the input signal, where 1<=J<=X, or a sub-sequence having the length J which is a one-to-one representation thereof being stored in the circuit.
Claim 3
Dependent Claim
111 words
A sequential finite-state machine circuit as claimed in claim 1, characterized in that the N bistable elements are presettable, the circuit being provided with (X-1) further bistable elements, coupled as a shift register, for the storage of the (X-1) most recent values of the input signal or values which are a one-to-one representation thereof, and is also provided with decoding logic, fed by the input signal and the (X-1) bistable elements of the shift register, which logic forms a detection signal as regards the occurrence of the given sequence of X values of the input signal, said detection signal being applied as a preset signal to the N presettable bistable elements.
Claim 4
Dependent Claim
136 words
A sequential finite-state machine circuit as claimed in claim 1, where X>=N, characterized in that the circuit comprises (X-N) further bistable elements FF(N+1), . . . , FF(X), and additional combinatory logic which, in response to the occurrence of the sub-sequence {c(0), c(1), . . . , c(J-1)}, having the length J, of the given sequence of X values of the input signal, where 1<=J<=X, each time makes the first J bistable elements FF(1), . . . , FF(J) assume a representation sequence of J values which is a one-to-one representation of said sub-sequence, the assignment of representations to states of the finite state machine being such that the states are represented by combinations of logic values of the bistable elements which correspond, as regards the first J values, to the representation sequences of J values.
Claim 5
Dependent Claim
152 words
A sequential-finite state machine circuit as claimed in claim 1, where X>=N, characterized in that the circuit comprises (X-N) further bistable elements for the storage of the (X-N) most recent values of the input signal, or values which are a one-to-one representation thereof, the circuit also comprising additional logic which, in response to the occurrence of a sub-sequence {c(0), c(1), . . . , c(J-1)}, having the length J, of the given sequence of X values of the input signal, where X-N<J<=X, each time makes the first J-X+N bistable elements FF(1), . . . , FF(J-X+N) assume a representation sequence of J-X+N values which is a one-to-one representation of said sub-sequence, the assignment of representations to states of the finite-state machine being such that the states are represented by combinations of logic values of the bistable elements which correspond, as regards the first J-X+N values, to the representation sequences of J-X+N values.
Claim 6
Dependent Claim
165 words
A sequential finite state machine circuit as claimed in claim 1, where X<N, characterized in that the circuit comprises additional logic which, in response to the occurrence of a sub-sequence {c(0), c(1), . . . , c(J-1)}, having the length J, of the given sequence of X values of the input signal, where 1<=J<=X, each time makes the first J bistable elements FF(1), . . . , FF(J) assume a representation sequence of J which is a one-to-one representation of said sub-sequence, the assignment of representations to states of the finite state machine being such that the states are represented by combinations of logic values of the bistable elements which correspond, as regards the first J values, to the representation sequences of J values, the additional logic making, in response to the occurrence of the whole sequence of X values of the input signal, the bistable elements FF(X+1), . . . , FF(N) assume values which correspond to the logic values of the rest state.
Claim 7
Dependent Claim
14 words
An integrated circuit comprising a sequential finite-state machine circuit as claimed in claim 1.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-03-17 | 1995-09-16 | 1996-03-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-03-17 | 1999-09-16 | 2000-03-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-03-17 | 2003-09-16 | 2004-03-17 | $7700.00 | Window Closed / Lapsed |