Patent US1180512A successfully refreshed from Google Patents.
Patent US5095483A successfully refreshed from Google Patents.
US5095483A
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Signature analysis in physical modeling
Assignee: International Business Machines Corp
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Filing: 1991-07-26
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Granted: 1992-03-10
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Expires: 2011-07-26
Abstract
Abstract In performing a series of device evaluation cycles relative to pins of a physical electronic model, a signature associated with an immediately preceding device evaluation cycle is compared to the corresponding signature that exists just prior to the last pattern for the current device evaluation cycle. If the signatures compare, the new pattern of the current evaluation cycle is completed. If the signatures do not compare, an error has occurred and the operator is notified so that this series of device evaluation cycles will not be considered valid. Computer simulation information is employed to determine the optimal times to clock signatures with each signal pin having its own programmable clocking circuit. These optimally generated signatures are used to verify the consistent operation of the physical model.
Inventors
- 👤 James F. Dubler
- 👤 Steven G. Robinson
- 👤 David A. Valashinas
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 13:56
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/26; G06F11/273; G06F11/277
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
140 words
In a system for simulating or testing an electronic device including a physical model, a method for assuring integrity of a series of device evaluation cycles, comprising: a) automatically generating a first signature summation of bits from a first pin of said model in response to application of a first set of patterns to said model; b) appending another pattern to said first set of patterns to form a second set of patterns; c) automatically generating a second signature summation of bits from said first pin of said model in response to application of said second set of patterns to said model before said another pattern is applied to said model during a next device evaluation cycle; and d) comparing said first signature summation of bits to said second signature summation of bits prior to application of said another pattern.
Claim 2
Dependent Claim
140 words
In a system for simulating or testing an electronic device including a physical model, a method for assuring integrity of a series of device evaluation cycles, comprising: a) automatically generating a first signature summation of bits from a first pin of said model in response to application of a first set of patterns to said model; b) appending another pattern to said first set of patterns to form a second set of patterns; c) automatically generating a second signature summation of bits from said first pin of said model in response to application of said second set of patterns to said model before said another pattern is applied to said model during a next device evaluation cycle; and d) comparing said first signature summation of bits to said second signature summation of bits prior to application of said another pattern.
Claim 3
Dependent Claim
22 words
The method of claim 1 further comprising: e) repeating steps a)-d) a predefined number of times if said comparing is not true.
Claim 4
Dependent Claim
17 words
The method of claim 2 further comprising: f) halting steps a)-d) if said predefined number is reached.
Claim 5
Dependent Claim
21 words
The method of claim 3 wherein each of said patterns includes signature clock generation data for providing generation of said signatures.
Claim 6
Dependent Claim
17 words
The method of claim 4 wherein said signature clock generation data is derived from simulation signal values.
Claim 7
Dependent Claim
29 words
The method of claim 4 wherein said clock generation data is included with each of said patterns when said pin is at a stable one or zero logic state.
Claim 8
Dependent Claim
166 words
In a system for simulating or testing an electronic device including a physical model, the improvement for assuring integrity of a series of device evaluation cycles, comprising: a) first means for automatically generating a first signature summation of bits from a first pin of said model in response to application of a first set of patterns to said model; b) means connected to said first means for appending another pattern to said first set of patterns to form a second set of patterns; c) second means connected to said first means for automatically generating a second signature summation of bits from said first pin of said model in response to application of said second set of patterns to said model before said another pattern is applied to said model during a next model evaluation cycle; and d) means connected to said first and second means for comparing said first signature summation of bits to said second signature summation of bits prior to applying said another pattern.
Claim 9
Dependent Claim
166 words
In a system for simulating or testing an electronic device including a physical model, the improvement for assuring integrity of a series of device evaluation cycles, comprising: a) first means for automatically generating a first signature summation of bits from a first pin of said model in response to application of a first set of patterns to said model; b) means connected to said first means for appending another pattern to said first set of patterns to form a second set of patterns; c) second means connected to said first means for automatically generating a second signature summation of bits from said first pin of said model in response to application of said second set of patterns to said model before said another pattern is applied to said model during a next model evaluation cycle; and d) means connected to said first and second means for comparing said first signature summation of bits to said second signature summation of bits prior to applying said another pattern.
Claim 10
Dependent Claim
21 words
The system of claim 7 wherein each of said patterns includes signature clock generation data for providing generation of said signatures.
Claim 11
Dependent Claim
17 words
The system of claim 8 wherein said signature clock generation data is derived from simulation signal values.
Claim 12
Dependent Claim
29 words
The system of claim 8 wherein said clock generation data is included with each of said patterns when said pin is at a stable one or zero logic state.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-03-10 | 1995-09-09 | 1996-03-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-03-10 | 1999-09-09 | 2000-03-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-03-10 | 2003-09-09 | 2004-03-10 | $7700.00 | Window Closed / Lapsed |