Patent US2463993A successfully refreshed from Google Patents.
Patent US5095346A successfully refreshed from Google Patents.
US5095346A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Stacked-capacitor for a dram cell
Assignee: Samsung Electronics Co Ltd
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Filing: 1990-08-31
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Granted: 1992-03-10
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Expires: 2010-08-31
Abstract
Abstract There is disclosed a stacked capacitor with high capacity which ensures structural stability in a DRAM cell and a method for manufacturing the same. The stacked-capacitor is of a hollow (or cylindrical) capacitor where both ends of several polysilicon layers which form a storage electrode are connected with each other. In construction, this inventive stacked-capacitor includes: a first polysilicon layer coupled to the source region so as to extend in parallel with surface of the substrate over the left and right sides of the source region; a bridge polysilicon layer, extending in the upward direction of the substrate from both ends of the first polysilicon layer; a dielectric film formed so as to contact with the surfaces of the bridge polysilicon layer, first polysilicon layer, second polysilicon layer; and a third polysilicon layer formed so as to contact with the surface of the dielectric film.
Inventors
- 👤 Dong-Joo Bae
- 👤 Won-Shik Baek
- 👤 Kyu-Hyun Choi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 05:28
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/31; H10B12/318; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10B12/036; H10P; H10P14/00; H10P14/40; H10P14/416
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
163 words
A DRAM cell having an element separating oxide film, a source region having left and right sides and a drain region which are formed on a semiconductor substrate, and a stacked capacitor comprising: a first polysilicon layer coupled to the source region and having left and right ends so as to respectively extend in parallel with a surface of the substrate over the left and right sides of said source region; a bridge polysilicon layer, extending in an upward direction of the substrate from both ends of said first polysilicon layer; a second polysilicon layer which makes contact with an upper end of the bridge polysilicon layer and extends in parallel with said first polysilicon layer; a dielectric film formed so as to contact with an inner surface and an outer surface of said bridge polysilicon layer, said first polysilicon layer, and said second polysilicon layer; and a third polysilicon layer formed so as to contact with a surface of said dielectric film.
Claim 2
Dependent Claim
163 words
A DRAM cell having an element separating oxide film, a source region having left and right sides and a drain region which are formed on a semiconductor substrate, and a stacked capacitor comprising: a first polysilicon layer coupled to the source region and having left and right ends so as to respectively extend in parallel with a surface of the substrate over the left and right sides of said source region; a bridge polysilicon layer, extending in an upward direction of the substrate from both ends of said first polysilicon layer; a second polysilicon layer which makes contact with an upper end of the bridge polysilicon layer and extends in parallel with said first polysilicon layer; a dielectric film formed so as to contact with an inner surface and an outer surface of said bridge polysilicon layer, said first polysilicon layer, and said second polysilicon layer; and a third polysilicon layer formed so as to contact with a surface of said dielectric film.
Claim 3
Dependent Claim
25 words
The DRAM cell according to claim 1, wherein said bridge polysilicon layer, first polysilicon layer and second polysilicon layer are formed into one storage electrode.
Claim 4
Dependent Claim
17 words
The DRAM cell according to claim 1, wherein said third polysilicon layer serves as a plate electrode.
Claim 5
Dependent Claim
28 words
The DRAM cell according to claim 1, wherein said bridge polysilicon layer is a part to which said first polysilicon layer and said second polysilicon layer are connected.
Claim 6
Dependent Claim
90 words
A stacked capacitor in a DRAM cell having a storage electrode and a plate electrode, said storage electrode comprising: a first polysilicon layer, coupled to a source region in a semiconductor substrate, having two ends extending over said source region; a bridge polysilicon layer extending upwards from said two ends of said first polysilicon layer; a second polysilicon layer connected to an upper end of said bridge polysilicon layer and extending in parallel with said first polysilicon layer; and a dielectric film separating said storage electrode from said plate electrode.
Claim 7
Dependent Claim
90 words
A stacked capacitor in a DRAM cell having a storage electrode and a plate electrode, said storage electrode comprising: a first polysilicon layer, coupled to a source region in a semiconductor substrate, having two ends extending over said source region; a bridge polysilicon layer extending upwards from said two ends of said first polysilicon layer; a second polysilicon layer connected to an upper end of said bridge polysilicon layer and extending in parallel with said first polysilicon layer; and a dielectric film separating said storage electrode from said plate electrode.
Claim 8
Dependent Claim
23 words
The stacked capacitor in a DRAM cell as claimed in claim 5, wherein said plate electrode is comprised of a third polysilicon layer.
Claim 9
Dependent Claim
24 words
The stacked capacitor in a DRAM cell as claimed in claim 5, wherein said dielectric film contacts an inner surface of said storage cell.
Claim 10
Dependent Claim
24 words
The stacked capacitor in a DRAM cell as claimed in claim 5, wherein said dielectric film contacts an outer surface of said storage cell.
Claim 11
Dependent Claim
24 words
The stacked capacitor in a DRAM cell as claimed in claim 8, wherein said dielectric film contacts an inner surface of said storage cell.
References Cited (Backward Citations)
US4673969A
Cited
JPS59167051A
Cited
JPS60137051A
Cited
US4926223A
Cited
US4700457A
Cited
JPS61231753A
Cited
JPS6298765A
Cited
US4899203A
Cited
JPH01289154A
Cited
US4864464A
Cited
US5006481A
Cited
US5005103A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-03-10 | 1995-09-09 | 1996-03-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-03-10 | 1999-09-09 | 2000-03-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-03-10 | 2003-09-09 | 2004-03-10 | $7700.00 | Window Closed / Lapsed |