Fabricating a narrow width EEPROM with single diffusion electrode formation

Claim 1

A method of making an MOS floating gate transistor cell comprising, disposing field oxide at least partially in a substrate to define opposed, spaced apart, linear barrier walls for a transistor, placing, in a single step, parallel, spaced apart doped regions in the substrate within the barrier walls in a parallel, linear pattern extending from one field oxide wall to an opposed field oxide wall, diffusing the doped regions to form source and drain electrodes having sides in abutment with opposed field oxide barrier walls, the spaced apart distance between the source and drain forming a channel, forming a thin oxide layer with surrounding dielectric over the drain electrode, with the thin oxide having linear boundaries, the thin oxide being thinner than the surrounding oxide forming an insulation layer over said source and drain electrodes and channel, said thin oxide formed within specified aligning tolerances and at a distance γ from the channel, and within specified line resolution tolerances of etching said thicker insulating layer over drain electrode, the thin oxide having a length dimension Z, forming a floating gate electrode atop the thin oxide, and channel within specified aligning tolerances, said floating gate overlapping said opposed barrier walls by a dimension α, overlapping said drain electrode beyond said thin oxide by a dimension β, overlapping said source electrode by a dimension δ, and forming a control electrode in insulated relation over the floating gate electrode.

Claim 2

A method of making an MOS floating gate transistor cell comprising, disposing field oxide at least partially in a substrate to define opposed, spaced apart, linear barrier walls for a transistor, placing, in a single step, parallel, spaced apart doped regions in the substrate within the barrier walls in a parallel, linear pattern extending from one field oxide wall to an opposed field oxide wall, diffusing the doped regions to form source and drain electrodes having sides in abutment with opposed field oxide barrier walls, the spaced apart distance between the source and drain forming a channel, forming a thin oxide layer with surrounding dielectric over the drain electrode, with the thin oxide having linear boundaries, the thin oxide being thinner than the surrounding oxide forming an insulation layer over said source and drain electrodes and channel, said thin oxide formed within specified aligning tolerances and at a distance γ from the channel, and within specified line resolution tolerances of etching said thicker insulating layer over drain electrode, the thin oxide having a length dimension Z, forming a floating gate electrode atop the thin oxide, and channel within specified aligning tolerances, said floating gate overlapping said opposed barrier walls by a dimension α, overlapping said drain electrode beyond said thin oxide by a dimension β, overlapping said source electrode by a dimension δ, and forming a control electrode in insulated relation over the floating gate electrode.