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US5091885A
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US
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Dynamic type random-access memory having improved timing characteristics
Assignee: Toshiba Corp
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Filing: 1990-05-15
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Granted: 1992-02-25
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Expires: 2010-05-15
Abstract
Abstract A dynamic type random-access memory includes a bit line pair constituted by first and second bit lines, a memory cell array constituted by a plurality of memory cells (MC i : i=0 to 255) connected to the bit line pair, a precharge circuit for precharging the bit line pair to a predetermined potential at a predetermined timing, a bit line sense amplifier to be enabled after data written in one of the plurality of memory cells (MC i : i=0 to 255) is read out to the bit line pair, and a charge transfer circuit connected between the bit line pair and first and second sense nodes of the bit line sense amplifier, turned off upon reception of a charge transfer drive signal which is decreased from a power source potential to a medium potential betwen the power source potential and a ground potential when a small potential difference is produced between bit lines of the bit line pair, and having an impedance decreased as a potential difference between the bit line pair and the first and second sense nodes of the bit line sense amplifier is increased when a potential difference between a control terminal and the first and second sense nodes exceeds a threshold value.
Inventors
- 👤 Takashi Ohsawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 23:36
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4091; G11C11/4094
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
212 words
A dynamic type random-access memory comprising: a bit line pair constituted by first and second bit lines; a memory cell array constituted by a plurality of memory cells connected to said bit line pair; a precharge circuit for precharging said bit line pair to a predetermined potential at a predetermined timing; a bit line sense amplifier to be enabled after data written in one of said plurality of memory cells is read out to said bit line pair; and a charge transfer circuit connected between said bit line pair and first and second sense nodes of said bit line sense amplifier, said dynamic type random-access memory including means for turning off said charge transfer circuit responsive to a reception of a charge transfer drive signal produced when a small potential difference is produced between bit lines of said bit line pair, and including means for decreasing an impedance responsive to a potential difference between said bit line pair and said first and second sense nodes of said bit line sense amplifier being increased when a potential difference between a control terminal and said first and second sense nodes or a potential difference between one of said bit line pair and one of said first and second sense nodes exceeds a threshold value.
Claim 2
Dependent Claim
212 words
A dynamic type random-access memory comprising: a bit line pair constituted by first and second bit lines; a memory cell array constituted by a plurality of memory cells connected to said bit line pair; a precharge circuit for precharging said bit line pair to a predetermined potential at a predetermined timing; a bit line sense amplifier to be enabled after data written in one of said plurality of memory cells is read out to said bit line pair; and a charge transfer circuit connected between said bit line pair and first and second sense nodes of said bit line sense amplifier, said dynamic type random-access memory including means for turning off said charge transfer circuit responsive to a reception of a charge transfer drive signal produced when a small potential difference is produced between bit lines of said bit line pair, and including means for decreasing an impedance responsive to a potential difference between said bit line pair and said first and second sense nodes of said bit line sense amplifier being increased when a potential difference between a control terminal and said first and second sense nodes or a potential difference between one of said bit line pair and one of said first and second sense nodes exceeds a threshold value.
Claim 3
Dependent Claim
111 words
A memory according to claim 1, wherein said charge transfer circuit includes means for changing an impedance when a potential difference between a first terminal of said first and second bit lines and a second terminal of said first and second nodes changes, and including means for turning off said charge transfer circuit when a potential difference between a third terminal and one of said first and second terminals becomes not less than a predetermined value, and including means for temporarily turning off said charge transfer circuit when a small potential difference is produced between said first and second bit lines when said data is read out from said memory cell.
Claim 4
Dependent Claim
30 words
A memory according to claim 1, wherein said charge transfer circuit is a field effect transistor, a predetermined drive signal being supplied to the gate of said field effect transistor.
Claim 5
Dependent Claim
82 words
A memory according to claim 1, wherein said field effect transistor is an n-channel MOS transistor, and including means for decreasing the level of a drive signal to be supplied to the gates of said MOS transistor from the power source potential to the medium potential between the power source potential and the ground potential in order to turn off said MOS transistor and including means for increasing the level of said drive signal in order to turn on said MOS transistor.
Claim 6
Dependent Claim
84 words
A memory according to claim 1, wherein said field effect transistor is a p-channel MOS transistor, said field effect transistor including means for increasing the level of a drive signal to be supplied to the gate of said MOS transistor from the ground potential to the medium potential between the power source potential and the ground potential in order to turn off said MOS transistor and including means for decreasing the level of said drive signal in order to turn on said MOS transistor.
Claim 7
Dependent Claim
41 words
A memory according to claim 1, wherein said charge transfer circuit is constituted by connecting a diode and a switch circuit in parallel with each other, said switch circuit being controlled responsive to the enabling of said bit line sense amplifier.
References Cited (Backward Citations)
US4852064A
Cited
US4933905A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-02-24 | 1995-08-26 | 1996-02-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-02-24 | 1999-08-26 | 2000-02-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-02-24 | 2003-08-26 | 2004-02-25 | $7700.00 | Window Closed / Lapsed |