US5091853A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Chained addressing mode pipelined processor which merges separately decoded parts of a multiple operation instruction
Assignee: Mitsubishi Electric Corp
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Filing: 1989-02-22
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Granted: 1992-02-25
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Expires: 2009-02-22
Abstract
Abstract A data processor of the present invention adopts a multi-stage indirect (chained) addressing mode, and merges pipeline processing units which are generated with respect to each designation of the chained addressing mode into a pipeline processing unit expressing the operation information for the operand of the instruction after completion of address calculation, thereby processing loads at each stage are equalized and processing speed as a whole apparatus increases.
Inventors
- 👤 Tetsuya Watanabe
- 👤 Toyohiko Yoshida
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 08:08
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/34; G06F9/355; G06F9/30145; G06F9/30149; G06F9/3016; G06F9/30167; G06F9/35
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
268 words
A data processor for processing an instruction by a pipeline processing mechanism, the instruction including a first operation information designating part for designating a part of an operand operation content, a second operation information designating part for designating a part of the operand operation content, and an addressing mode designating part for specifying information relating to an operand address, comprising: a first pipeline stage for decoding a particular instruction by dividing said particular instruction into a plurality of unit decoding processings and for outputting a decoding result of each unit decoding processing, said first pipeline stage decoding said first operation information designating part as a first unit decoding processing to output the first unit decoding result, and decoding said second operation information designating part and said addressing mode designating part as a second unit decoding processing to output the second unit decoding result; a second pipeline stage for calculating the operand addresses according to each said decoding result to output said operand address and for successively merging a part of or all of a plurality of each said decoding results into a unit processing to output said operation information of an operand as a merged operation information, said second pipeline stage merging information relating to operand operation included in said first unit decoding result and said second unit decoding result into unit processing to output said operation information of an operand as a operand operation information, and for calculating an operand address according to said second unit decoding result to output said operand address; and a third pipeline stage which fetches an operand according to said operand address.
Claim 2
Dependent Claim
268 words
A data processor for processing an instruction by a pipeline processing mechanism, the instruction including a first operation information designating part for designating a part of an operand operation content, a second operation information designating part for designating a part of the operand operation content, and an addressing mode designating part for specifying information relating to an operand address, comprising: a first pipeline stage for decoding a particular instruction by dividing said particular instruction into a plurality of unit decoding processings and for outputting a decoding result of each unit decoding processing, said first pipeline stage decoding said first operation information designating part as a first unit decoding processing to output the first unit decoding result, and decoding said second operation information designating part and said addressing mode designating part as a second unit decoding processing to output the second unit decoding result; a second pipeline stage for calculating the operand addresses according to each said decoding result to output said operand address and for successively merging a part of or all of a plurality of each said decoding results into a unit processing to output said operation information of an operand as a merged operation information, said second pipeline stage merging information relating to operand operation included in said first unit decoding result and said second unit decoding result into unit processing to output said operation information of an operand as a operand operation information, and for calculating an operand address according to said second unit decoding result to output said operand address; and a third pipeline stage which fetches an operand according to said operand address.
Claim 3
Independent Claim
170 words
A method for processing an instruction having a first operation information designating part, a second operation information designating part and an addressing mode designating part, said processing method comprising the steps of: providing a pipeline processing mechanism including a dividing and decoding pipeline stage, an operand address calculation and merging pipeline stage and an operand fetch pipeline stage responsive to said operand address; dividing each instruction into a plurality of unit decoding processings; decoding the first operation information designating part of each divided instruction at said dividing and decoding pipeline stage to provide a first unit decoding result; decoding the second operation information designating part and the addressing mode designating part of each divided instruction at said dividing and decoding pipeline stage to provide a second unit decoding processing; merging operand operation information from each said first unit decoding result and said second decoding result; calculating an operand address responsive to said second unit decoding result; and fetching an operand responsive to said operand operation information and said operand address.
Claim 4
Independent Claim
170 words
A method for processing an instruction having a first operation information designating part, a second operation information designating part and an addressing mode designating part, said processing method comprising the steps of: providing a pipeline processing mechanism including a dividing and decoding pipeline stage, an operand address calculation and merging pipeline stage and an operand fetch pipeline stage responsive to said operand address; dividing each instruction into a plurality of unit decoding processings; decoding the first operation information designating part of each divided instruction at said dividing and decoding pipeline stage to provide a first unit decoding result; decoding the second operation information designating part and the addressing mode designating part of each divided instruction at said dividing and decoding pipeline stage to provide a second unit decoding processing; merging operand operation information from each said first unit decoding result and said second decoding result; calculating an operand address responsive to said second unit decoding result; and fetching an operand responsive to said operand operation information and said operand address.
Claim 5
Dependent Claim
151 words
A pipelined data processor, comprising: a first pipeline stage for decoding an instruction by dividing said instruction into a first processing unit and a second processing unit, with said first processing unit including a first operation information designating part of said instruction and said second processing unit including a second operation information designating part and an addressing mode designating part of said instruction, said first pipeline stage successively decoding said first processing unit and said second processing unit to produce successive first and second decoding results; and a second pipeline stage, coupled to said first pipeline stage, for calculating operand addresses responsive to each successive decoding result of said first stage, and for merging operand operation information of said first and said second decoding results into an operand operation information of said instruction, said second pipeline stage calculating an operand address for the instruction responsive to said merged operand operation information.
Claim 6
Dependent Claim
151 words
A pipelined data processor, comprising: a first pipeline stage for decoding an instruction by dividing said instruction into a first processing unit and a second processing unit, with said first processing unit including a first operation information designating part of said instruction and said second processing unit including a second operation information designating part and an addressing mode designating part of said instruction, said first pipeline stage successively decoding said first processing unit and said second processing unit to produce successive first and second decoding results; and a second pipeline stage, coupled to said first pipeline stage, for calculating operand addresses responsive to each successive decoding result of said first stage, and for merging operand operation information of said first and said second decoding results into an operand operation information of said instruction, said second pipeline stage calculating an operand address for the instruction responsive to said merged operand operation information.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-02-24 | 1995-08-26 | 1996-02-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-02-24 | 1999-08-26 | 2000-02-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-02-24 | 2003-08-26 | 2004-02-25 | $7700.00 | Window Closed / Lapsed |