Patent US5089986A successfully refreshed from Google Patents.
US5089986A
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Mushroom double stacked capacitor
Assignee: Micron Technology Inc
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Filing: 1991-01-02
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Granted: 1992-02-18
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Expires: 2011-01-02
Abstract
Abstract A mushroom double stacked capacitor (mushroom cell) using a modified stacked capacitor storage cell fabrication process. The mushroom cell is made up of polysilicon structure, having a mushroom extended V-shaped cross-section. The storage node plate of the mushroom cell is overlaid by polysilicon with a dielectric sandwiched in between and connects to an access device's active area via a buried contact. The plate extends to an adjacent storage node but is isolated from the adjacent node by less than the critical resolution dimension of a given lithographic technology. The shape of the polysilicon structure increases storage capability 200% or more without enlarging the surface area defined for a normal buried digit line stacked capacitor cell.
Inventors
- 👤 Gurtej S. Sandhu
- 👤 Pierre C. Fazan
- 👤 Yauh-Ching Liu
- 👤 Hiang C. Chan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 02:09
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/31; H10B12/318
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
211 words
A DRAM memory array constructed on a silicon substrate, said memory array comprising: a plurality of active areas arranged in parallel interdigitated rows and parallel non-interdigitated columns, said active areas separated by isolation means, each of said active areas having a digit line junction, and a storage node junction; a plurality of parallel conductive word lines aligned along said rows such that a digit line junction and a storage node junction within each active area are bridged by a word line, each word line being insulated from associated active areas by a gate dielectric layer; a plurality of parallel conductive digit lines, aligned along said columns such that a digit line makes electrical contact with each digit line junction within a column, said digit lines running perpendicular to and over said word lines forming a 3-dimensional, waveform-like topology, said digit and word lines electrically separated from one another by isolation means; and at least one storage capacitor for each active area, each capacitor having a storage node plate that is in electrical contact with its associated active area and a cell plate that is common to the entire array, each storage node plate being insulated from said cell plate by a capacitive dielectric layer and having a mushroom extended V-shaped cross-section.
Claim 2
Dependent Claim
211 words
A DRAM memory array constructed on a silicon substrate, said memory array comprising: a plurality of active areas arranged in parallel interdigitated rows and parallel non-interdigitated columns, said active areas separated by isolation means, each of said active areas having a digit line junction, and a storage node junction; a plurality of parallel conductive word lines aligned along said rows such that a digit line junction and a storage node junction within each active area are bridged by a word line, each word line being insulated from associated active areas by a gate dielectric layer; a plurality of parallel conductive digit lines, aligned along said columns such that a digit line makes electrical contact with each digit line junction within a column, said digit lines running perpendicular to and over said word lines forming a 3-dimensional, waveform-like topology, said digit and word lines electrically separated from one another by isolation means; and at least one storage capacitor for each active area, each capacitor having a storage node plate that is in electrical contact with its associated active area and a cell plate that is common to the entire array, each storage node plate being insulated from said cell plate by a capacitive dielectric layer and having a mushroom extended V-shaped cross-section.
Claim 3
Dependent Claim
167 words
The memory array of claim 1, wherein said capacitor comprises: a conductively-doped first polysilicon layer, said first polysilicon layer conforming to said waveform-like topology having a plurality of peaks and valleys, said first polysilicon layer forming a V-shaped component having first and second ends, said first polysilicon layer making contact to said storage node junction at said first end with said second end being isolated from an adjacent active area by thick oxide; a conductively doped second polysilicon layer attaching to said first polysilicon layer, thereby extending said first polysilicon V-shaped component into a mushroom extended V-shaped component, thereby forming said storage node plate; an insulation layer of said capacitator dielectric being adjacent to said storage node plate and coextensive therewith except at regions for said contact at said first end and said isolation at said second end; and a conductively-doped third polysilicon layer forming said cell plate, said cell plate having upper and lower surfaces and being adjacent to said capacitor dielectric layer and coextensive therewith.
Claim 4
Dependent Claim
19 words
A structure as recited in claim 2, wherein said first and said second polysilicon have a rugged, textured surface.
References Cited (Backward Citations)
US4896293A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1995-02-17 | 1995-08-19 | 1996-02-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-02-17 | 1999-08-19 | 2000-02-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-02-17 | 2003-08-19 | 2004-02-18 | $7700.00 | Window Closed / Lapsed |