Charge domain vector-matrix product processing system

Claim 1

A charge domain vector-matrix product network for generating the signals representative of the product of an N-element vector and an N×K element matrix comprising: A. a charge coupled device (CCD) N-stage tapped delay line, including: means for establishing a succession of N charge packets therein in response to a succession of N applied input signals, each of said packets having a magnitude corresponding to one of the elements of said vector. means for shifting said charge packets from stage-to-stage along said delay line, and N floating gate sensing electrodes, each of said electrodes overlying one of said stages and being adapted to provide a potential thereon representative of the magnitude of a charge package currently within its underlying stage, B. an N×K M-bit digital parallel shift register memory device adapted for storing N×K M-bit words, each of said words being representative of the value of a corresponding element of said matrix, wherein said shift register memory device includes K stages in a stack configuration, each stage including means for storing N M-bit words, and including means responsive to an applied shift signal for selectively shifting said stored words from stage-to-stage from an input stage to an output stage in said stack, C. N M-bit charge domain digital-analog multipliers, each of said multipliers including means for generating a charge packet therein having a magnitude proportional to the product of a potential applied to an analog input port thereof and an M-bit digital signal applied to a digital input port thereof, wherein the analog input port of each of said multipliers is coupled to an associated sensing electrode of said delay line, and the digital input port of each of said multipliers is coupled to an associated M-bit portion of said output stage said shift register memory device, and D. a controller for successively applying in parallel N words from said output stage of said shift register memory device to the respective digital input ports of said multipliers, where each set of N words includes the words representative of the values of one of the rows of said matrix, said controller including means for generating said shift signals and for applying said shift signals to said shift register memory device whereby said N words are shifted from stage to stage therein, E. a charge summing device operative for each set of N words applied to said multipliers, including means for generating in succession an output charge packet for each of said sets, each output charge packet having a magnitude proportional to the sum of the magnitude of the charge packets generated by said multipliers for said set, wherein the magnitudes the respective output charge packets correspond to the respective elements of said vector-matrix product.