Merged CCD/MOS integrated circuit

Claim 2

An integrated circuit for providing multi-bit parallel multiplication or multi-bit parallel division, comprising: a substrate; digital input means located on the substrate for receiving a plurality of digital input bits to be processed by the integrated circuit; charge-coupled device means located on the substrate and including a plurality of full adder cells arranged in a two-dimensional array of sequential stages, with sum and carry output bits from each stage being channel to predetermined full adder cells of the next sequential stage, if any; metal-oxide semiconductor means located on the substrate for selectively channeling certain of the digital input bits to multiple stages of the two-dimensional array of full adder cells in accordance with other of the digital input bits; and digital output means located on the substrate for outputting a plurality of digital output bits produced by the plurality of full adder cells.

Claim 3

An integrated circuit as defined in claim 1, wherein: the integrated circuit is a multi-bit parallel multiplier; the digital input means receives a multi-bit multiplier and a multi-bit multiplicand; and the plurality of full adder cells in the charge-coupled device means form a rectangular array, with each row of the array adding a prescribed multi-bit word to the multi-bit sum from an adjacent row of the array, to produce a new multi-bit sum.

Claim 4

An integrated circuit as defined in claim 2, wherein: the multi-bit parallel multiplier implements Booth's algorithm; and the metal-oxide semiconductor means selectively delays and processes the multi-bit multiplicand and channels a corresponding multi-bit word to each row of the full adder array.

Claim 5

An integrated circuit as defined in claim 3, wherein the metal-oxide semiconductor means processes the multi-bit multiplicand in accordance with particular bits of the multi-bit multiplier, such that the prescribed multi-bit word channeled to each row of the full adder array is either the multiplicand shifted by one bit, the complement of the multiplicand shifted by one bit, the multiplicand itself, the complement of the multiplicand, or a word containing all zero bits.

Claim 6

An integrated circuit as defined in claim 1, wherein: the integrated circuit is a multi-bit parallel divider; the digital input means receives a multi-bit dividend and a multi-bit divisor; and the plurality of full adder cells in the charge-coupled device means form a rectangular array, with each row of the array subtracting a prescribed multi-bit word from the multi-bit difference produced by an adjacent row of the array, to produce a new multi-bit difference.

Claim 7

An integrated circuit as defined in claim 1, wherein the charge-coupled device means is arranged such that charge paths interconnecting the plurality of full adder cells do not cross over each other.

Claim 8

A parallel radix-4 digital multiplier integrated circuit comprising: a substrate; digital input means located on the substrate for receiving a multi-bit multiplier and a multi-bit multiplicand to be multiplier together by the integrated circuit; a sequential array of charge-coupled device full adder stages located on the substrate, each stage transferring sum and carry bits to the next succeeding stage; metal-oxide semiconductor recoder means located on the substrate for processing the multi-bit multiplier and generating a plurality of control signals based thereon; metal-oxide semiconductor selector means, located on the substrate and responsive to the control signals and to the multi-bit multiplicand, for channeling selected bits of the multiplicand to multiple stages of the array of full adder stages; wherein the full adder stages operate on the selected bits channeled to them and the sum and carry its transferred between successive stages, to produce a multi-bit product; digital means located on the substrate for outputting the multi-bit product produced by the array of full adder stages; and wherein the array of full adder stages is arranged such that none of the charge paths interconnecting the individual full adder stage cross over each other.

Claim 9

A parallel radix-4 digital multiplier integrated circuit comprising: a substrate; digital input means located on the substrate for receiving a multi-bit multiplier and a multi-bit multiplicand to be multiplier together by the integrated circuit; a sequential array of charge-coupled device full adder stages located on the substrate, each stage transferring sum and carry bits to the next succeeding stage; metal-oxide semiconductor recoder means located on the substrate for processing the multi-bit multiplier and generating a plurality of control signals based thereon; metal-oxide semiconductor selector means, located on the substrate and responsive to the control signals and to the multi-bit multiplicand, for channeling selected bits of the multiplicand to multiple stages of the array of full adder stages; wherein the full adder stages operate on the selected bits channeled to them and the sum and carry its transferred between successive stages, to produce a multi-bit product; digital means located on the substrate for outputting the multi-bit product produced by the array of full adder stages; and wherein the array of full adder stages is arranged such that none of the charge paths interconnecting the individual full adder stage cross over each other.

Claim 10

A parallel radix-4 digital multiplier integrated circuit as defined in claim 7, wherein: the circuit implements Booth's algorithm; and the prescribed bits channeled by the selector means to the successive full adder stages correspond to at least one of the multiplicand shifted by one bit or its complement, the multiplicand itself or its complement, a word containing all zero bits.