US4446532A
Expired / Lapsed
US
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Surface charge signal processing apparatus
Assignee: Lockheed Martin Corp
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Filing: 1982-02-03
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Granted: 1984-05-01
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Expires: 2002-02-03
Abstract
Abstract A plurality of charge storage cells, each including first and second storage regions and corresponding first and second electrodes insulatingly overlying the storage regions are provided in a semiconductor substrate. Means are provided for introducing into each of the first charge storage regions a respective quantity of charge proportional to a respective sample of an analog signal. Means are provided for developing a plurality of voltage waveforms, each of the waveforms including a series of periods, and each period constituted of first and second subperiods. Means are provided for applying each of the voltage waveforms to a respective one of the second electrodes of the cells. A high absolute level of a waveform applied to a second electrode of a cell causing charge in the first storage region thereof to transfer to the second storage region thereof and a low absolute level of the waveform applied to a second electrode of a cell causing charge in the second storage region thereof to transfer to the first storage region thereof. Each of the waveforms has a low absolute level during a first subperiod and an absolute level which is either high or low during a second subperiod in response to a respective reference signal, whereby charge in each cell is transferred between the first and second charge storage regions thereof in a time sequence determined by a respective reference signal. Means are provided connected in circuit with the first storage electrodes for sensing the total net charge transferred to and from the first charge storage regions during a common period of the voltage waveforms.
Inventors
- 👤 Richard D. Baertsch
- 👤 William E. Engeler
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 19:06
CPC Classifications
G; G06; G06G; G06G7/00; G06G7/12; G06G7/19; G06G7/1907
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
749 words
A waveform generator comprising: a plurality of stages, each stage having an input terminal, a first output terminal and a second output terminal, the first output terminal of one stage being connected to the input terminal of a succeeding stage, each stage including first and second substages, each substage including first, second, third and fourth transistors, each transistor including a source, drain and a gate, first, second and third clocking lines, the source-drain conduction paths of the first, second and third transistors of the first and second substages of each stage being connected in series between said first clocking line and the second output terminal of said stage, the source-drain conduction path of said fourth transistor of each substage being connected in parallel with the source drain conduction path of said first transistor of said substage, the gate of the fourth transistor of the first substage of a first stage of said plurality of stages being connected to the input terminal of said first stage, an input terminal of said waveform generator being connected to said input terminal of said first stage, a first nodal capacitance being provided between the conductive junction of said first and second transistors of each substage and ground, a second nodal capacitance being provided between the conductive junction of said second and third transistors of each substage and ground, a third nodal capacitance being provided between said second output terminal of each stage and ground, the conductive junction of the second and third transistors of the first substage of each stage being connected to the gate of the fourth transistor of the second substage of said stage, the conductive junction of the second and third transistors of the second substage of each stage being connected to the first output terminal of said stage, said first clocking line being connected to the gate of the first transistor of each of said substages, said second clocking line being connected to the gates of the second and third transistors of the first substage of each of said stages, said third clocking line being connected to the gates of the second and third transistors of the second substage of each of said stages, means for applying a first clocking voltage between said first clocking line and ground, said first clocking voltage having a high level during a first subperiod of each period thereof and a low level during a second subperiod of each period thereof, means for applying a second clocking voltage between said second line and ground, said second clocking voltage having a high level during the first subperiod of a period of said first clocking voltage extending from the initiation of said high level and terminating during the second subperiod of said first period of said first clocking voltage, said second clocking voltage having a low level during the remainder of said second subperiod and during a succeeding second period of said first clocking voltage, means for applying a third clocking voltage between said third line and ground, said third clocking voltage having a high level during the first subperiod of a succeeding second period of said first clocking voltage extending from the initiation of said high level and terminating during the second subperiod of said second period of said first clocking voltage, said second clocking voltage having a low level during the remainder of said second subperiod of said second period and during a succeeding third period of said first clocking voltage, whereby when a high level of signal is applied to the input terminal of a stage during a first period of the first clocking voltage, an output signal is produced at the second output terminal of said stage which has a high level during the first subperiod of the first period of said first clocking voltage, a low level during the second subperiod of said first period and a high level during the succeeding second period of said first clocking voltage and when a low level of signal is applied to the input terminal of a stage during a first period and a succeeding second period of the first clocking voltage, an output signal is produced at the second output terminal of said stage which has a high level during the first period of said first clocking voltage, a high level during the first subperiod of the succeeding second period of said first clocking voltage and a low level during the second subperiod of the succeeding second period of said first clocking voltage.
Claim 2
Dependent Claim
749 words
A waveform generator comprising: a plurality of stages, each stage having an input terminal, a first output terminal and a second output terminal, the first output terminal of one stage being connected to the input terminal of a succeeding stage, each stage including first and second substages, each substage including first, second, third and fourth transistors, each transistor including a source, drain and a gate, first, second and third clocking lines, the source-drain conduction paths of the first, second and third transistors of the first and second substages of each stage being connected in series between said first clocking line and the second output terminal of said stage, the source-drain conduction path of said fourth transistor of each substage being connected in parallel with the source drain conduction path of said first transistor of said substage, the gate of the fourth transistor of the first substage of a first stage of said plurality of stages being connected to the input terminal of said first stage, an input terminal of said waveform generator being connected to said input terminal of said first stage, a first nodal capacitance being provided between the conductive junction of said first and second transistors of each substage and ground, a second nodal capacitance being provided between the conductive junction of said second and third transistors of each substage and ground, a third nodal capacitance being provided between said second output terminal of each stage and ground, the conductive junction of the second and third transistors of the first substage of each stage being connected to the gate of the fourth transistor of the second substage of said stage, the conductive junction of the second and third transistors of the second substage of each stage being connected to the first output terminal of said stage, said first clocking line being connected to the gate of the first transistor of each of said substages, said second clocking line being connected to the gates of the second and third transistors of the first substage of each of said stages, said third clocking line being connected to the gates of the second and third transistors of the second substage of each of said stages, means for applying a first clocking voltage between said first clocking line and ground, said first clocking voltage having a high level during a first subperiod of each period thereof and a low level during a second subperiod of each period thereof, means for applying a second clocking voltage between said second line and ground, said second clocking voltage having a high level during the first subperiod of a period of said first clocking voltage extending from the initiation of said high level and terminating during the second subperiod of said first period of said first clocking voltage, said second clocking voltage having a low level during the remainder of said second subperiod and during a succeeding second period of said first clocking voltage, means for applying a third clocking voltage between said third line and ground, said third clocking voltage having a high level during the first subperiod of a succeeding second period of said first clocking voltage extending from the initiation of said high level and terminating during the second subperiod of said second period of said first clocking voltage, said second clocking voltage having a low level during the remainder of said second subperiod of said second period and during a succeeding third period of said first clocking voltage, whereby when a high level of signal is applied to the input terminal of a stage during a first period of the first clocking voltage, an output signal is produced at the second output terminal of said stage which has a high level during the first subperiod of the first period of said first clocking voltage, a low level during the second subperiod of said first period and a high level during the succeeding second period of said first clocking voltage and when a low level of signal is applied to the input terminal of a stage during a first period and a succeeding second period of the first clocking voltage, an output signal is produced at the second output terminal of said stage which has a high level during the first period of said first clocking voltage, a high level during the first subperiod of the succeeding second period of said first clocking voltage and a low level during the second subperiod of the succeeding second period of said first clocking voltage.
Claim 3
Dependent Claim
41 words
The waveform generator of claim 1 including: a plurality of inverters, each having an input terminal connected to the second output terminal of a respective one of said stages and an output terminal constituting the output terminal of said waveform generator.
Claim 4
Dependent Claim
19 words
The waveform generator of claim 2 in which each of said inverters is constituted of a plurality of transistors.
Claim 5
Dependent Claim
120 words
The waveform generator of claim 2 including: means for providing a reference word having a series of successive elements, each of said elements having either a high level or a low level of a duration equal to two of said periods of said first clocking voltages, means for applying said reference word to the input terminal of said waveform generator, whereby a plurality of output voltage waveforms are produced, each at a respective output terminal of said waveform generator, the output voltage waveform produced at an output terminal of said waveform generator being identical to the voltage waveform produced at a preceding one of said output terminals except delayed by the duration of two periods of said first clocking voltage.
Claim 6
Dependent Claim
17 words
The waveform generator of claim 1 in which said transistors are formed on a common semiconductor substrate.
Claim 7
Dependent Claim
17 words
The waveform generator of claim 3 in which said transistors are formed on a common semiconductor substrate.
Claim 8
Dependent Claim
94 words
The waveform generator of claim 5 in which said first nodal capacitance is the capacitance of the drain of said first transistor and the source of said second transistor with respect to said substrate, said second nodal capacitance is the capacitance of the drain of said second transistor and the source of said third transistor with respect to said substrate, said third nodal capacitance is the capacitance of the drain of said third transistor of said first stage and the capacitance of said third transistor of said second substrage with respect to said substrate.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-05-01 | 1987-10-31 | 1988-05-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-05-01 | 1991-10-31 | 1992-05-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-05-01 | 1995-10-31 | 1996-05-01 | $7700.00 | Window Closed / Lapsed |