US4084257A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Signal processing apparatus
Assignee: General Electric Co
•
Filing: 1977-05-19
•
Granted: 1978-04-11
•
Expires: 1997-05-19
Abstract
Abstract An analog memory apparatus for storing and retrieving a sequence of samples of an analog signal is described. The apparatus includes a plurality of storage devices each storing each of the samples of the sequence with appropriate sign in accordance with a predetermined code. The samples stored in each device represent a respective algebraic sum of the samples of the sequence. To retrieve the samples of the analog signal the different algebraic sums of samples stored in the devices are algebraically summed in accordance with the predetermined code.
Inventors
- 👤 Hubert K. Burke
- 👤 Gerald J. Michon
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 17:04
CPC Classifications
G; G06; G06G; G06G7/00; G06G7/12; G06G7/14; G11; G11C; G11C27/00; G11C27/04
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
385 words
Signal processing apparatus comprising a substrate of semiconductor material of one type conductivity having a major surface, first means forming a plurality of first charge storage regions for opposite type carriers adjacent said major surface of said substrate, second means forming a plurality of second charge storage regions for opposite type carriers adjacent said major surface of said substrate, each coupled to a respective first charge storage region to form a plurality of first storage cells, third means forming a plurality of third charge storage regions for opposite type carriers adjacent said major surface of said substrate, fourth means forming a plurality of fourth charge storage regions for opposite type carriers adjacent said major surface of said substrate, each coupled to a respective third charge storage region to form a plurality of second charge storage cells, each of said first charge storage cells being paired with a respective one of said second charge storage cells, a first row conductor line, a second row conductor line and a plurality of column conductor lines, said first means including a plurality of first electrodes, each insulatingly overlying a respective one of said first storage regions, said second means including a plurality of second electrodes, each insulatingly overlying a respective one of said second storage regions and each connected to said first row line, said third means including a plurality of third electrodes, each insulatingly overlying a respective one of said third storage regions, said fourth means including a plurality of fourth electrodes, each insulatingly overlying a respective one of said fourth storage regions and each connected to said second row line, the first and third electrodes of each of said pairs of first and second storage cells being connected to a respective column line, a plurality of charge introduction means, each associated with a respective one of said pairs of said first and second storage cells, each of said charge introduction means developing a sequence of packets of charge in response to an analog signal, each packet of charge of said sequence being proportional to a respective sample of said analog signal, corresponding packets of charge of said sequences of packets being substantially identical, each of said charge introduction means including means for transferring a packet of charge alternatively into the cells of a respective pair of cells.
Claim 2
Dependent Claim
385 words
Signal processing apparatus comprising a substrate of semiconductor material of one type conductivity having a major surface, first means forming a plurality of first charge storage regions for opposite type carriers adjacent said major surface of said substrate, second means forming a plurality of second charge storage regions for opposite type carriers adjacent said major surface of said substrate, each coupled to a respective first charge storage region to form a plurality of first storage cells, third means forming a plurality of third charge storage regions for opposite type carriers adjacent said major surface of said substrate, fourth means forming a plurality of fourth charge storage regions for opposite type carriers adjacent said major surface of said substrate, each coupled to a respective third charge storage region to form a plurality of second charge storage cells, each of said first charge storage cells being paired with a respective one of said second charge storage cells, a first row conductor line, a second row conductor line and a plurality of column conductor lines, said first means including a plurality of first electrodes, each insulatingly overlying a respective one of said first storage regions, said second means including a plurality of second electrodes, each insulatingly overlying a respective one of said second storage regions and each connected to said first row line, said third means including a plurality of third electrodes, each insulatingly overlying a respective one of said third storage regions, said fourth means including a plurality of fourth electrodes, each insulatingly overlying a respective one of said fourth storage regions and each connected to said second row line, the first and third electrodes of each of said pairs of first and second storage cells being connected to a respective column line, a plurality of charge introduction means, each associated with a respective one of said pairs of said first and second storage cells, each of said charge introduction means developing a sequence of packets of charge in response to an analog signal, each packet of charge of said sequence being proportional to a respective sample of said analog signal, corresponding packets of charge of said sequences of packets being substantially identical, each of said charge introduction means including means for transferring a packet of charge alternatively into the cells of a respective pair of cells.
Claim 3
Dependent Claim
36 words
The apparatus of claim 1 in which the number of packets of charge in each of said sequences of packets of charge is equal to the number of said pairs of first and second storage cells.
Claim 4
Dependent Claim
86 words
The apparatus of claim 1 including means for storing packets of charge in each pair of said pairs of first and second storage cells to represent a respective algebraic sum of the packets of said sequence including: means for transferring packets of charge to be read out with one sign in each pair of cells to the first storage cells thereof, means for transferring packets of charge to be read out with the opposite sign in each pair of cells to the second storage cells thereof.
Claim 5
Dependent Claim
117 words
The apparatus of claim 3 including means for deriving a signal proportional to the algebraic sum of the packets of a sequence stored in a pair of said first and second storage cells including: means for initially storing the packets of said sequence in the first storage region and the third storage region of said pair of storage cells and thereafter transferring the packets of said sequence to respective second and fourth storage regions of said pair of storage cells, means for sensing the difference in the signal induced on the second electrode and the signal induced on the fourth electrode of said pair of cells in response to the transfer of the packets of said sequence.
Claim 6
Dependent Claim
117 words
The apparatus of claim 3 including means for deriving a signal proportional to the algebraic sum of the packets of a sequence stored in a pair of said first and second storage cells including: means for initially storing the packets of said sequence in the second storage region and the fourth storage region of said pair of storage cells and thereafter transferring the packets of said sequence to respective first and third storage regions of said pair of storage cells, means for sensing the difference in the signal induced on the second electrode and the signal induced on the fourth electrode of said pair of cells in response to the transfer of the packets of said sequence.
Claim 7
Dependent Claim
119 words
The apparatus of claim 3 including means for deriving a signal proportional to the algebraic sums of the algebraic sums of the packets of said sequences stored in said pairs of first and second storage cells including: means for initially storing the packets of said sequences in the first storage regions and the third storage regions of said pairs of storage cells and thereafter transferring the packets of said sequences to respective second and fourth storage regions of said pairs of storage cells, means for sensing the difference in the signals induced on said second electrodes and the signals induced on said fourth electrodes of said pairs of cells in response to the transfer of packets of said sequences.
Claim 8
Dependent Claim
119 words
The combination of claim 3 including means for deriving a signal proportional to the algebraic sums of the algebraic sums of the packets of said sequences stored in said pairs of first and second storage cells including: means for initially storing the packets of said sequences in the second storage regions and the fourth storage regions of said pairs of storage cells and thereafter transferring the packets of said sequences to respective first and third storage regions of said pairs of storage cells, means for sensing the difference in the signals induced on said second electrodes and the signals induced on said fourth electrodes of said pairs of cells in response to the transfer of packets of said sequences.
Claim 9
Dependent Claim
32 words
The apparatus of claim 3 in which each algebraic sum of the packets of a respective sequence is in accordance with the signs of a respective row of a cylical binary matrix.
Claim 10
Dependent Claim
65 words
The apparatus of claim 6 in which each algebraic sum of the packets of a respective sequence is in accordance with the signs of a respective row of an orthogonal cyclical binary matrix and in which each algebraic sum of the algebraic sums of the packets of said sequences is in accordance with the signs of a respective column of said orthogonal cylical binary matrix.
Claim 11
Dependent Claim
243 words
In combination, a substrate of semiconductor material of one type conductivity having a major surface, first means forming a first charge storage region for opposite type carriers adjacent said major surface of said substrate, second means forming a second charge storage region for opposite type carriers adjacent said major surface of said substrate and coupled to said first charge storage region to form a first storage cell, third means forming a third charge storage region for opposite type carriers adjacent said major surface of said substrate, fourth means forming a fourth charge storage region for opposite type carriers adjacent said major surface of said substrate and coupled to said third charge storage region to form a second charge storage cell, said first means including a first electrode insulatingly overlying said first storage region, and each connected to said first row line, said second means including a second electrode insulatingly overlying a said second storage region, said third means including a third electrode insulatingly overlying said third storage region, said fourth means including a fourth electrode insulatingly overlying a said fourth storage region and connected to said second electrode, a charge introduction means for developing a sequence of packets of charge in response to an analog signal, each packet of charge of said sequence being proportional to a respective sample of said analog signal, said charge introduction means including means for transferring a packet of charge alternatively into said first and second storage cells.
Claim 12
Dependent Claim
243 words
In combination, a substrate of semiconductor material of one type conductivity having a major surface, first means forming a first charge storage region for opposite type carriers adjacent said major surface of said substrate, second means forming a second charge storage region for opposite type carriers adjacent said major surface of said substrate and coupled to said first charge storage region to form a first storage cell, third means forming a third charge storage region for opposite type carriers adjacent said major surface of said substrate, fourth means forming a fourth charge storage region for opposite type carriers adjacent said major surface of said substrate and coupled to said third charge storage region to form a second charge storage cell, said first means including a first electrode insulatingly overlying said first storage region, and each connected to said first row line, said second means including a second electrode insulatingly overlying a said second storage region, said third means including a third electrode insulatingly overlying said third storage region, said fourth means including a fourth electrode insulatingly overlying a said fourth storage region and connected to said second electrode, a charge introduction means for developing a sequence of packets of charge in response to an analog signal, each packet of charge of said sequence being proportional to a respective sample of said analog signal, said charge introduction means including means for transferring a packet of charge alternatively into said first and second storage cells.
Claim 13
Dependent Claim
343 words
Signal processing apparatus comprising a substrate of semiconductor material of one type conductivity having a major surface, first means forming a plurality of first charge storage regions for opposite type carriers adjacent said major surface of said substrate, second means forming a plurality of second charge storage regions for opposite type carriers adjacent said major surface of said substrate, each coupled to a respective first charge storage region to form a plurality of first storage cells, third means forming a plurality of third charge storage regions for opposite type carriers adjacent said major surface of said substrate, fourth means forming a plurality of fourth charge storage regions for opposite type carriers adjacent said major surface of said substrate, each coupled to a respective third charge storage region to form a plurality of second charge storage cells, each of said first charge storage cells being paired with a respective one of said second charge storage cells, said first means including a plurality of first electrodes, each insulatingly overlying a respective one of said first storage regions, said second means including a plurality of second electrodes, each insulatingly overlying a respective one of said second storage regions and each connected to said conductive line, said third means including a plurality of third electrodes, each insulatingly overlying a respective one of said third storage regions, said fourth means including a plurality of fourth electrodes, each insulatingly overlying a respective one of said fourth storage regions and each connected to said conductive line, a plurality of charge introduction means, each associated with a respective one of said pairs of said first and second storage cells, each of said charge introduction means developing a sequence of packets of charge in response to an analog signal, each packet of charge of said sequence being proportional to a respective sample of said analog signal, corresponding packets of charge of said sequence of packets being substantially identical, each of said charge introduction means including means for transferring a packet of charge alternatively into the cells of a respective pair of cells.
Claim 14
Dependent Claim
343 words
Signal processing apparatus comprising a substrate of semiconductor material of one type conductivity having a major surface, first means forming a plurality of first charge storage regions for opposite type carriers adjacent said major surface of said substrate, second means forming a plurality of second charge storage regions for opposite type carriers adjacent said major surface of said substrate, each coupled to a respective first charge storage region to form a plurality of first storage cells, third means forming a plurality of third charge storage regions for opposite type carriers adjacent said major surface of said substrate, fourth means forming a plurality of fourth charge storage regions for opposite type carriers adjacent said major surface of said substrate, each coupled to a respective third charge storage region to form a plurality of second charge storage cells, each of said first charge storage cells being paired with a respective one of said second charge storage cells, said first means including a plurality of first electrodes, each insulatingly overlying a respective one of said first storage regions, said second means including a plurality of second electrodes, each insulatingly overlying a respective one of said second storage regions and each connected to said conductive line, said third means including a plurality of third electrodes, each insulatingly overlying a respective one of said third storage regions, said fourth means including a plurality of fourth electrodes, each insulatingly overlying a respective one of said fourth storage regions and each connected to said conductive line, a plurality of charge introduction means, each associated with a respective one of said pairs of said first and second storage cells, each of said charge introduction means developing a sequence of packets of charge in response to an analog signal, each packet of charge of said sequence being proportional to a respective sample of said analog signal, corresponding packets of charge of said sequence of packets being substantially identical, each of said charge introduction means including means for transferring a packet of charge alternatively into the cells of a respective pair of cells.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-04-10 | 1981-10-10 | 1982-04-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-04-10 | 1985-10-10 | 1986-04-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-04-10 | 1989-10-10 | 1990-04-11 | $7700.00 | Window Closed / Lapsed |