Delay circuit having one of a plurality of delay lines which may be selected to provide an operation of a ring oscillator

Claim 2

Delay apparatus for receiving an input signal and providing a delayed version of the input signal, the actual delay between the input signal and the delayed version being controlled to remain near a desired delay, comprising: an integrated circuit comprising: a first voltage controlled delay circuit having an input line for receiving the input signal, an output line for generating the delayed version of the input signal, and a control input line for receiving a control voltage for controlling the length of the actual delay, a second voltage controlled delay circuit having the same physical and electrical configuration as the first delay circuit, the control input line of the second delay line being connected to the control input line of the first delay circuit, an inverter, connected between the output and the input of the second delay circuit to cause the second delay circuit to oscillate at a frequency determined by the delay period of the second delay circuit, buffer circuitry connected to the output of the second delay circuit for providing a periodic reference signal having a frequency representative of the frequency of oscillation of the second delay circuit, and conversion circuitry for receiving a digital value indicative of the desired delay and in response thereto providing a control voltage to the control input line of the first and second delay circuits; and off-ship control circuitry, separate from the integrated circuit, for receiving the periodic reference signal and in response thereto computing the digital value, and transmission circuitry for transmitting the digital value from the off-chip control circuit to the conversion circuitry.

Claim 3

The delay apparatus of claim 1 wherein the off-chip control circuitry receives a periodic reference signal from each of a plurality of oscillating delay circuits, and in response to each periodic signal, provides a corresponding digital value for maintaining the frequency of the periodic signal within a desired range.

Claim 4

The delay apparatus of claim 2 wherein the off-chip control circuit serially transmits each digital value to corresponding conversion circuitry.

Claim 5

The apparatus of claim 1 in which the inverter may selectively be disconnected from the second delay circuit to enable the second delay circuit to operate as a delay line.

Claim 6

The delay apparatus of claim 1 wherein the conversion circuitry includes a digital-to-analog converter whose output is the control voltage and whose input is the digital value indicative of the desired delay.

Claim 7

The delay apparatus of claim 5 wherein the conversion circuitry further includes a serial-in, parallel-out shift register for receiving the digital value serially from the off-chip control circuitry and delivering the digital value in parallel to the digital-to-analog converter.

Claim 8

The apparatus of claim 1 in which the off-chip control circuitry includes a counter to count the pulses of the received periodic reference signal.

Claim 9

Delay apparatus for receiving an input signal and providing a delayed version of the input signal, the actual delay between the input signal and the delayed version being controlled to remain near a desired delay, comprising: an integrated circuit comprising: a first voltage controlled delay circuit having an input line for receiving the input signal, an output line for generating the delayed version of the input signal, and a control input line for receiving a control voltage for controlling the length of the actual delay, a second voltage controlled delay circuit having the same physical and electrical configuration as the first delay circuit, the control input line of the second delay line being connected to the control input line of the first delay circuit, an inverter, connected between the output and the input of the second delay circuit to cause the second delay circuit to oscillate at a frequency determined by the delay period of the second delay circuit, circuitry for selectively disconnecting the inverter from the second delay circuit to enable the second delay circuit to operate as a delay line, buffer circuitry connected to the output of the second delay circuit for providing a periodic reference signal having a frequency representative of the frequency of oscillation of the second delay circuit, conversion circuitry for receiving a digital value indicative of the desired delay and in response thereto providing a control voltage to the control input line of the first and second delay circuits, said conversion circuitry including a digital-to-analog converter whose output is the control voltage and whose input is the digital value indicative of the desired delay, said conversion circuitry further including a serial-in, parallel-out shift register for receiving the digital value serially from the off-chip control circuitry and delivering the digital value in parallel to the digital-to-analog converter, and off-chip control circuitry, separate from the integrated circuit, for receiving the periodic reference signal and in response thereto computing the digital value, said off-chip control circuitry including a counter to count the pulses of the received periodic reference signal, and transmission circuitry for transmitting the digital value from the off-chip control circuit to the conversion circuitry.

Claim 10

Delay apparatus for receiving an input signal and providing a delayed version of the input signal, the actual delay between the input signal and the delayed version being controlled to remain near a desired delay, comprising: an integrated circuit comprising: a first voltage controlled delay circuit having an input line for receiving the input signal, an output line for generating the delayed version of the input signal, and a control input line for receiving a control voltage for controlling the length of the actual delay, a second voltage controlled delay circuit having the same physical and electrical configuration as the first delay circuit, the control input line of the second delay line being connected to the control input line of the first delay circuit, an inverter, connected between the output and the input of the second delay circuit to cause the second delay circuit to oscillate at a frequency determined by the delay period of the second delay circuit, circuitry for selectively disconnecting the inverter from the second delay circuit to enable the second delay circuit to operate as a delay line, buffer circuitry connected to the output of the second delay circuit for providing a periodic reference signal having a frequency representative of the frequency of oscillation of the second delay circuit, conversion circuitry for receiving a digital value indicative of the desired delay and in response thereto providing a control voltage to the control input line of the first and second delay circuits, said conversion circuitry including a digital-to-analog converter whose output is the control voltage and whose input is the digital value indicative of the desired delay, said conversion circuitry further including a serial-in, parallel-out shift register for receiving the digital value serially from the off-chip control circuitry and delivering the digital value in parallel to the digital-to-analog converter, and off-chip control circuitry, separate from the integrated circuit, for receiving the periodic reference signal and in response thereto computing the digital value, said off-chip control circuitry including a counter to count the pulses of the received periodic reference signal, and transmission circuitry for transmitting the digital value from the off-chip control circuit to the conversion circuitry.