US5084913A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Programmable multi-mode two-channel timing generator
Assignee: Unisys Corp
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Filing: 1990-07-26
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Granted: 1992-01-28
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Expires: 2010-07-26
Abstract
Abstract A novel universal multi-mode programmable two-channel timing generator employs a plurality of counters and logic circuitry. An input chip counter is coupled for receiving system clock signals and producing chip strobe and other output timing signals which are programmably capable of generating different rates of operation and different data or PN rates on different channels as well as different I and O enable signals for dedicated tracking and timing signals. The signals produced are used for synchronous-sample or non-synchronous-sample operation in a simple fast acting circuit designed for VLSI implementation.
Inventors
- 👤 Samuel C. Kingston
- 👤 Steven T. Barham
- 👤 Harold L. Simonsen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 15:17
CPC Classifications
H; H04; H04B; H04B1/00; H04B1/69; H04B1/707
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
157 words
A programmable digital multi-mode timing generator of the type used in a communications receiver having a system clock signal recovered from a data stream, comprising: chip counter means having an input adapted to receive said system clock signal and produce a lower frequency rate chip strobe signal, I channel counter means having an input coupled to said chip strobe signal for producing an output I PN strobe signal employed to synchronize the operation of the communications receiver system to the I spreading rate of the received data, I PN per data counter means having an input coupled to said I PN strobe signal for producing an I data bit rate strobe signal employed to synchronize the operation of the communications receiver system to the I data bit rate of the received data, and programmable means in said timing generator counter means for setting the number of I PN strobe signals in said data bit rate strobe signal.
Claim 2
Dependent Claim
157 words
A programmable digital multi-mode timing generator of the type used in a communications receiver having a system clock signal recovered from a data stream, comprising: chip counter means having an input adapted to receive said system clock signal and produce a lower frequency rate chip strobe signal, I channel counter means having an input coupled to said chip strobe signal for producing an output I PN strobe signal employed to synchronize the operation of the communications receiver system to the I spreading rate of the received data, I PN per data counter means having an input coupled to said I PN strobe signal for producing an I data bit rate strobe signal employed to synchronize the operation of the communications receiver system to the I data bit rate of the received data, and programmable means in said timing generator counter means for setting the number of I PN strobe signals in said data bit rate strobe signal.
Claim 3
Dependent Claim
106 words
A programmable digital timing generator as set forth in claim 1 which further includes Q channel counter means having an input coupled to said chip strobe signal for producing an output Q PN strobe signal, employed to synchronize the operation of a communications receiver system to the Q spreading rate of the received data, and Q PN per data counter means having an input coupled to said Q PN strobe signal for producing a Q data bit rate strobe signal employed to synchronize the operation of the I and/or Q channels of a communications receiver system to the Q data bit rate of the received data.
Claim 4
Dependent Claim
61 words
A programmable digital timing generator as set forth in claim 2 wherein said programmable means in said I channel counter means, said I PN per data counter means, said Q channel counter means and said Q PN per data counter means are coupled to external means for programming different spreading rates and/or different data rates on said I and Q channels.
Claim 5
Dependent Claim
81 words
A programmable digital timing generator as set forth in claim 2 further includes a programmable means further a programmable PN reset synchronizing logic circuit means having a plurality of information input signals and a reset I PN and a reset Q PN output signal coupled as inputs to said I channel counter means and said Q channel counter means respectively for programmably initializing said channel counter means for generating offset or non offset spreading I PN and Q PN strobe signals.
Claim 6
Dependent Claim
82 words
A programmable digital timing generator as set forth in claim 4 which further includes a programmable PN per data counter means having a plurality of information input signal and an I data reset and a Q data reset output signal coupled to said I PN per data counter means and to said Q PN data counter means respectively for programmably initializing said I PN per data counter means and Q PN per data counter means for generating offset and non offset data.
Claim 7
Dependent Claim
49 words
A programmable digital timing generator as set forth in claim 1 which further includes dedicated I PN circuit means having a plurality of programmable inputs and an I PN strobe input for producing dedicated I PN dedicated enable signals for use by the receiver for dedicated I channel tracking.
Claim 8
Dependent Claim
51 words
A programmable digital timing generator as set forth in claim 2 which further includes dedicated Q PN circuit means having a plurality of programmable inputs and a Q PN strobe input for producing dedicated Q PN dedicated enable signals for use by the receiver for dedicated I and/or Q channel tracking.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-01-27 | 1995-07-29 | 1996-01-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-01-27 | 1999-07-29 | 2000-01-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-01-27 | 2003-07-29 | 2004-01-28 | $7700.00 | Window Closed / Lapsed |