Timing pulse generator for generating timing pulses synchronized with the horizontal synchronizing signal in a video signal

Claim 2

A timing pulse generator comprising: an input terminal receiving a gate pulse; a flip-flop having a set input portion, a clock input portion, an output portion and an inverted output portion and being set by said gate pulses in response to clock pulses applied to said clock input portion; an inverter inverting said gate pulses; a NAND gate receiving an output of said inverter and an inverted output from said inverted output portion of said flip-flop; an oscillator whose oscillation is controlled by an output of said NAND gate, said oscillator having an output portion and generating clock pulses at said output portion thereof; means for transferring said clock pulses to said clock input portion of said flip-flop to produce shaped gate pulses at said output portion of said flip-flop; and a counter receiving said clock pulses and counting said clock pulses, said counter being reset by said shaped gate pulses.

Claim 3

A timing pulse generator as claimed in claim 1, wherein said transferring means includes a binary flip-flop dividing a repetition frequency of said clock pulses.

Claim 4

A timing pulse generator as claimed in claim 1, wherein said transferring means includes a series connection of binary flip-flops dividing a repetition frequency of said clock pulses.

Claim 5

A timing pulse generator as claimed in claim 1, wherein said transferring means includes a connecting wire between an output portion of said oscillator and said clock input portion of said flip-flop.

Claim 6

A timing pulse generator as claimed in claim 1, wherein said oscillator generates said clock pulses having a repetition frequency 300 to 400 times higher than a repetition frequency of said gate pulses.

Claim 7

A timing pulse generator as claimed in claim 2, wherein said oscillator generates said clock pulses having a repetition frequency 300 to 400 times higher than a repetition frequency of said gate pulses.

Claim 8

A pulse generator comprising: an input terminal receiving gate pulses; a flip-flop being set by said gate pulses and having an output end and a clock input end; an OR gate receiving said gate pulses and an output produced at said output end of said flip-flop; an oscillator whose oscillation is controlled by an output of said OR gate, said oscillator generating clock pulses; a means for transferring said clock pulses to said clock input end of said flip-flop to clock said flip-flop; and a counter receiving said clock pulses and counting said clock pulses, said counter being reset by said output produced at said output end of said flip-flop.

Claim 9

A pulse generator comprising: an input terminal receiving gate pulses; a flip-flop being set by said gate pulses and having an output end and a clock input end; an OR gate receiving said gate pulses and an output produced at said output end of said flip-flop; an oscillator whose oscillation is controlled by an output of said OR gate, said oscillator generating clock pulses; a means for transferring said clock pulses to said clock input end of said flip-flop to clock said flip-flop; and a counter receiving said clock pulses and counting said clock pulses, said counter being reset by said output produced at said output end of said flip-flop.

Claim 10

A timing pulse generator comprising: an input terminal receiving horizontal synchronizing pulses contained in a video signal; a flip-flop having a clock input portion, an output portion and an inverted output portion and being set by said horizontal synchronizing pulses in response to clock pulses applied to said clock input portion; an inverter inverting said horizontal synchronizing pulses; a NAND gate receiving an output of said inverter and an inverted output from said inverted output portion of said flip-flop; an oscillator whose oscillation is controlled by an output of said NAND gate, said oscillator having an output portion at which clock pulses having a repetition frequency 300 to 400 times higher than a repetition frequency of said horizontal synchronizing pulses are generated; means for transferring said clock pulses to said clock input portion of said flip-flop to produce shaped gate pulses at said output portion of said flip-flop, said transferring means including a binary flip-flop dividing said clock pulses; and a counter receiving said clock pulses and counting said clock pulses, said counter being reset by said shaped gate pulses.

Claim 11

A timing pulse generator comprising: an input terminal receiving horizontal synchronizing pulses contained in a video signal; a flip-flop having a clock input portion, an output portion and an inverted output portion and being set by said horizontal synchronizing pulses in response to clock pulses applied to said clock input portion; an inverter inverting said horizontal synchronizing pulses; a NAND gate receiving an output of said inverter and an inverted output from said inverted output portion of said flip-flop; an oscillator whose oscillation is controlled by an output of said NAND gate, said oscillator having an output portion at which clock pulses having a repetition frequency 300 to 400 times higher than a repetition frequency of said horizontal synchronizing pulses are generated; means for transferring said clock pulses to said clock input portion of said flip-flop to produce shaped gate pulses at said output portion of said flip-flop, said transferring means including a binary flip-flop dividing said clock pulses; and a counter receiving said clock pulses and counting said clock pulses, said counter being reset by said shaped gate pulses.

Claim 12

A pulse generator comprising: an input terminal receiving gate pulses; a flip-flop being set by said gate pulses and having an output end and a clock input end; an OR gate receiving said gate pulses and an output produced at said output end of said flip-flop; an oscillator whose oscillation is controlled by an output of said OR gate, said oscillator generating clock pulses having a repetition frequency 300 to 400 times higher than said gate pulses; a means for transferring said clock pulses to said clock input end of said flip-flop to clock said flip-flop; and a counter receiving said clock pulses and counting said clock pulses, said counter being reset by said output produced at said output end of said flip-flop.

Claim 13

A pulse generator comprising: an input terminal receiving gate pulses; a flip-flop being set by said gate pulses and having an output end and a clock input end; an OR gate receiving said gate pulses and an output produced at said output end of said flip-flop; an oscillator whose oscillation is controlled by an output of said OR gate, said oscillator generating clock pulses having a repetition frequency 300 to 400 times higher than said gate pulses; a means for transferring said clock pulses to said clock input end of said flip-flop to clock said flip-flop; and a counter receiving said clock pulses and counting said clock pulses, said counter being reset by said output produced at said output end of said flip-flop.

Claim 14

A pulse generator comprising: an input terminal receiving gate pulses; a flip-flop being set by said gate pulses and having an output end and a clock input end; an OR gate receiving said gate pulses and an output produced at said output end of said flip-flop; an oscillator whose oscillation is controlled by an output of said OR gate, said oscillator generating clock pulses; a means for transferring said clock pulses to said clock input end of said flip-flop to clock said flip-flop, said transferring means including a binary flip-flop dividing said clock pulses to two; and a counter receiving said clock pulses and counting said clock pulses, said counter being reset by said output produced at said output end of said flip-flop.

Claim 15

A pulse generator comprising: an input terminal receiving gate pulses; a flip-flop being set by said gate pulses and having an output end and a clock input end; an OR gate receiving said gate pulses and an output produced at said output end of said flip-flop; an oscillator whose oscillation is controlled by an output of said OR gate, said oscillator generating clock pulses; a means for transferring said clock pulses to said clock input end of said flip-flop to clock said flip-flop, said transferring means including a binary flip-flop dividing said clock pulses to two; and a counter receiving said clock pulses and counting said clock pulses, said counter being reset by said output produced at said output end of said flip-flop.

Claim 16

A pulse generator comprising: an input terminal receiving gate pulses; a flip-flop being set by said gate pulses and having an output end and a clock input end; an OR gate receiving said gate pulses and an output produced at said output end of said flip-flop; an oscillator whose oscillation is controlled by an output of said OR gate, said oscillator generating clock pulses; a means for transferring said clock pulses to said clock input end of said flip-flop to clock said flip-flop, said transferring means including a series connection of binary flip-flops dividing said clock pulses; and a counter receiving said clock pulses and counting said clock pulses, said counter being reset by said output produced at said output end of said flip-flop.

Claim 17

A pulse generator comprising: an input terminal receiving gate pulses; a flip-flop being set by said gate pulses and having an output end and a clock input end; an OR gate receiving said gate pulses and an output produced at said output end of said flip-flop; an oscillator whose oscillation is controlled by an output of said OR gate, said oscillator generating clock pulses; a means for transferring said clock pulses to said clock input end of said flip-flop to clock said flip-flop, said transferring means including a series connection of binary flip-flops dividing said clock pulses; and a counter receiving said clock pulses and counting said clock pulses, said counter being reset by said output produced at said output end of said flip-flop.

Claim 18

A pulse generator comprising: an input terminal receiving gate pulses; a flip-flop being set by said gate pulses and having an output end and a clock input end; an OR gate receiving said gate pulses and an output produced at said output end of said flip-flop; an oscillator whose oscillation is controlled by an output of said OR gate, said oscillator generating clock pulses; a means for transferring said clock pulses to said clock input end of said flip-flop to clock said flip-flop, said transferring means including a connecting wire applying said clock pulses to said clock input end of said flip-flop; and a counter receiving said clock pulses and counting said clock pulses, said counter being reset by said output produced at said output end of said flip-flop.

Claim 19

A pulse generator comprising: an input terminal receiving gate pulses; a flip-flop being set by said gate pulses and having an output end and a clock input end; an OR gate receiving said gate pulses and an output produced at said output end of said flip-flop; an oscillator whose oscillation is controlled by an output of said OR gate, said oscillator generating clock pulses; a means for transferring said clock pulses to said clock input end of said flip-flop to clock said flip-flop, said transferring means including a connecting wire applying said clock pulses to said clock input end of said flip-flop; and a counter receiving said clock pulses and counting said clock pulses, said counter being reset by said output produced at said output end of said flip-flop.

Claim 20

A timing pulse generator comprising: an input terminal receiving gate pulses which have first and second potential levels; a gated clock oscillator generating clock pulses, said oscillator starting the oscillation in synchronism with said first potential level of said gate pulses; a counter receiving said clock pulses and counting said clock pulses; means responsive to said clock pulses for shaping the waveform of said gate pulses to produce shaped gate pulses having third and fourth potential levels; means for stopping the oscillation of said oscillator in response to a state where said gate pulses and said shaped gate pulses are respectively in said second potential level and said fourth potential level; and means for resetting said counter by the output of said shaping means in response to said fourth potential level of said shaped gate pulses.

Claim 21

A timing pulse generator comprising: an input terminal receiving gate pulses which have first and second potential levels; a gated clock oscillator generating clock pulses, said oscillator starting the oscillation in synchronism with said first potential level of said gate pulses; a counter receiving said clock pulses and counting said clock pulses; means responsive to said clock pulses for shaping the waveform of said gate pulses to produce shaped gate pulses having third and fourth potential levels; means for stopping the oscillation of said oscillator in response to a state where said gate pulses and said shaped gate pulses are respectively in said second potential level and said fourth potential level; and means for resetting said counter by the output of said shaping means in response to said fourth potential level of said shaped gate pulses.