Buffer device suitable for asynchronous transfer mode communication

Claim 1

A buffer device for receiving, temporarily storing and transmitting data accompanied by information indicating a priority level of the data, where there is at least two distinct priority levels, the device comprising: data register array including a plurality of data register means for temporarily storing the data, the data register means being divided into empty data register means storing no data and as many number of imaginary FIFO queues as a number of distinct priority levels, each imaginary FIFO queue being corresponding to each distinct priority level, and a number of data register means in each imaginary FIFO queue being flexible; administrative register array comprised of a two port RAM means for modifiably storing the administrative information containing pointer chains specifying the imaginary FIFO queues in the data register array, having a write-in port through which the administrative information can be written into the administrative register array and a read-out port through which the administrative information can be read out from the administrative register array which are independently operable; data input means for receiving new data, entering the new data into one empty data register means, and modifying the pointer chain specifying the imaginary FIFO queue corresponding to a priority level of the new data indicated by the information accompanying the new data, such that the pointer chain is extended to include that one empty data register means into which the new data is entered at an end of that imaginary FIFO queue; and data output means for taking out data stored in one data register means, transmitting the data, and modifying the pointer chain specifying the imaginary FIFO queue corresponding to a priority level of that data, such that the pointer chain is shortened to exclude that one data register means from which the data is taken from a top of that imaginary FIFO queue.