Patent US5079748A successfully refreshed from Google Patents.
US5079748A
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Dynamic random access memory with read-write signal of shortened duration
Assignee: Mitsubishi Electric Corp
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Filing: 1990-01-24
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Granted: 1992-01-07
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Expires: 2010-01-24
Abstract
Abstract A semiconductor dynamic RAM provided with an I/O load (5) rendered inactive during a writing cycle comprises a monostable multivibrator (16) for receiving a read/write indicating signal W for indicating reading and writing data from and into a memory cell (2) and outputting a signal We having a shorter duration than that of the signal W at down edge of the signal W as a trigger. The output signal We of the monostable multivibrator (16) is supplied as a control signal for rendering the I/O load (5) inactive.
Inventors
- 👤 Hideshi Miyatake
- 👤 Masaki Kumanoya
- 👤 Hideto Hidaka
- 👤 Hiroyuki Yamasaki
- 👤 Yasuhiro Konishi
- 👤 Yuto Ikeda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 15:54
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/4076
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
202 words
In a dynamic RAM device comprising a plurality of word lines and a plurality of bit line pairs interconnecting with said word lines, and memory cells at intersections of said word lines and said bit line pairs, addressing means for selecting a word line and a bit line pair to access a predetermined memory cell, I/O lines for supplying data to and obtaining data from said bit line pairs, write buffer means for supplying said I/O lines with a write voltage to be written as data into a selected memory cell, and I/O lines control means for connecting selectively a source of predetermined voltage to said I/O lines, means responsive to a leading edge of a read-write indicating signal (W) for generating an effective read-write signal (We) having a duration that is shorter than that of said read-write indicating signal (W), said write buffer means receiving said effective read-write signal (We) and supplying said write voltage to said I/O lines only during the duration of said effective read-write signal; and said I/O lines control means receiving said effective read-write signal (We) and isolating said I/O lines from said source of predetermined voltage only during the duration of said effective read-write signal (We).
Claim 2
Dependent Claim
202 words
In a dynamic RAM device comprising a plurality of word lines and a plurality of bit line pairs interconnecting with said word lines, and memory cells at intersections of said word lines and said bit line pairs, addressing means for selecting a word line and a bit line pair to access a predetermined memory cell, I/O lines for supplying data to and obtaining data from said bit line pairs, write buffer means for supplying said I/O lines with a write voltage to be written as data into a selected memory cell, and I/O lines control means for connecting selectively a source of predetermined voltage to said I/O lines, means responsive to a leading edge of a read-write indicating signal (W) for generating an effective read-write signal (We) having a duration that is shorter than that of said read-write indicating signal (W), said write buffer means receiving said effective read-write signal (We) and supplying said write voltage to said I/O lines only during the duration of said effective read-write signal; and said I/O lines control means receiving said effective read-write signal (We) and isolating said I/O lines from said source of predetermined voltage only during the duration of said effective read-write signal (We).
Claim 3
Dependent Claim
65 words
In the dynamic RAM device in accordance with claim 1, said read-write indicating signal having a predetermined duration, said I/O lines control means including means for isolating said I/O lines from said source of predetermined voltage during a first portion of the duration of said read-write indicating signal for precharging said I/O lines during a second portion of the duration of said read-write indicating signal.
Claim 4
Independent Claim
205 words
A method of writing data to a dynamic RAM device comprising a plurality of word lines and a plurality of bit line pairs intersecting with said word lines and memory cells at intersections of said word lines and said bit line pairs, means for receiving a read-write indicating signal (W), addressing means for selecting a word line and a bit line pair to access a predetermined memory cell, I/O lines for supplying data to and obtaining data from said bit lines pairs, write buffer means for supplying said I/O lines with a write voltage to be written as data into a selected memory cell and I/O lines control means for connecting selectively a source of predetermined voltage to said I/O lines, the method comprising the steps of: detecting a leading edge of said read-write indicating signal (W), and in response, generating an effective read-write signal (We) having a duration that is shorter than that of said read-write indicating signal (W); and, during only the duration of said effective read-write signal (We), (1) controlling said write buffer means to supply said write voltage to said I/O lines, and (2) controlling said I/O lines control means to isolate said I/O lines from said source of predetermined voltage.
Claim 5
Independent Claim
205 words
A method of writing data to a dynamic RAM device comprising a plurality of word lines and a plurality of bit line pairs intersecting with said word lines and memory cells at intersections of said word lines and said bit line pairs, means for receiving a read-write indicating signal (W), addressing means for selecting a word line and a bit line pair to access a predetermined memory cell, I/O lines for supplying data to and obtaining data from said bit lines pairs, write buffer means for supplying said I/O lines with a write voltage to be written as data into a selected memory cell and I/O lines control means for connecting selectively a source of predetermined voltage to said I/O lines, the method comprising the steps of: detecting a leading edge of said read-write indicating signal (W), and in response, generating an effective read-write signal (We) having a duration that is shorter than that of said read-write indicating signal (W); and, during only the duration of said effective read-write signal (We), (1) controlling said write buffer means to supply said write voltage to said I/O lines, and (2) controlling said I/O lines control means to isolate said I/O lines from said source of predetermined voltage.
Claim 6
Dependent Claim
58 words
The method of claim 3, wherein said read-write indicating signal has a predetermined duration, comprising the further steps of: isolating said I/O lines from said source of predetermined voltage during a first portion of the duration of said read-write indicating signal, and precharging said I/O lines during a second portion of the duration of said read-write indicating signal.
Claim 7
Independent Claim
200 words
A method of writing data to a dynamic RAM device comprising a plurality of word lines and a plurality of bit line pairs intersecting with said word lines and memory cells at intersections of said word lines and said bit line pairs, means for receiving a read-write indicating signal (W), addressing means for selecting a word line and a bit line pair to access a predetermined memory cell, I/O lines for supplying data to and obtaining data from said bit lines pairs and means for supplying a source of predetermined voltage to said I/O lines, the method comprising the steps of: detecting a leading edge of said read-write indicating signal (W) and in response, generating an effective read-write signal (We) having a duration that is shorter than that of said read-write indicating signal (W), and during only the duration of said effective read-write signal (We), (1) supplying a write voltage to said I/O lines, and (2) isolating said I/O lines from said source of predetermined voltage; and thereafter, controlling said addressing means to select a different memory cell, whereby said addressing means does not change the selection of said memory cells during the duration of the read-write indicating signal (W).
Claim 8
Independent Claim
200 words
A method of writing data to a dynamic RAM device comprising a plurality of word lines and a plurality of bit line pairs intersecting with said word lines and memory cells at intersections of said word lines and said bit line pairs, means for receiving a read-write indicating signal (W), addressing means for selecting a word line and a bit line pair to access a predetermined memory cell, I/O lines for supplying data to and obtaining data from said bit lines pairs and means for supplying a source of predetermined voltage to said I/O lines, the method comprising the steps of: detecting a leading edge of said read-write indicating signal (W) and in response, generating an effective read-write signal (We) having a duration that is shorter than that of said read-write indicating signal (W), and during only the duration of said effective read-write signal (We), (1) supplying a write voltage to said I/O lines, and (2) isolating said I/O lines from said source of predetermined voltage; and thereafter, controlling said addressing means to select a different memory cell, whereby said addressing means does not change the selection of said memory cells during the duration of the read-write indicating signal (W).
Claim 9
Dependent Claim
58 words
The method of claim 5, wherein said read-write indicating signal has a predetermined duration, comprising the further steps of: isolating said I/O lines from said source of predetermined voltage during a first portion of the duration of said read-write indicating signal, and precharging said I/O lines during a second portion of the duration of said read-write indicating signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-01-06 | 1995-07-08 | 1996-01-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-01-06 | 1999-07-08 | 2000-01-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-01-06 | 2003-07-08 | 2004-01-07 | $7700.00 | Window Closed / Lapsed |