Chip identification method for use with scan design systems and scan testing techniques

Claim 3

A method as recited in claim 1 wherein said plurality of predefined shift register latches (SRLs) in each LSI chip to be identified are located a predetermined number N of pad SRLs from a scan data output (SDO) of the LSI chip.

Claim 4

A method as recited in claim 2 wherein said step of selectively reading out said stored predetermined identification number to identify the LSI chip includes the steps of: detecting said predetermined number N of bit-shifts; said detected N bit-shifts corresponding to said pad SRLs from said SDO, and identifying said stored predetermined identification number responsive to said detected number N bit-shifts.

Claim 5

A method as recited in claim 1 wherein said step of storing said assigned predetermined identification number in a plurality of predefined shift register latches (SRLs) includes the steps of: identifying a predetermined number of pad shift register latches SRLs disposed between said predefined shift register latches (SRLs) in each LSI chip to be identified and a scan data output (SDO) of the LSI chip; and applying a signal to set each of said predefined shift register latches (SRLs) corresponding to said assigned predetermined identification number.

Claim 6

A method as recited in claim 4 wherein said step of applying a signal to set each of the predefined shift register latches (SRLs) corresponding to said assigned predetermined identification number includes the step of: applying a selected logical zero or logical one functional data signal to a functional data input D of each predefined SRL; and applying a system clock signal to load said applied functional data signal into each predefined SRL.

Claim 7

A method as recited in claim 5 wherein each said SRL consists of a L1 latch and a L2 latch, said L2 latch coupled to said L1 latch and having a B clock signal applied for copying data from said L1 latch to said L2 latch, and said L1 latch including said functional data input D, said L1 latch having a SDI for receiving data from a previous SRL L2 latch in a scan ring and having an A clock signal applied for copying data from said L2 latch to said L1 latch and wherein the step of selectively reading out said stored predetermined identification number to identify the LSI chip includes the steps of: activating a scan gate signal for disabling said system clock signal; activating a B clock signal for copying said applied functional data signal from said L1 latch to said L2 latch; and sequentially activating a first A clock signal and a second B clock signal and sampling a chip scan data output signal with each said activated first A clock signal.

Claim 8

Apparatus for uniquely identifying large scale integrated (LSI) circuit chips of the type conforming to scan design systems and testing techniques and having a plurality of shift register latches storage elements forming a scan ring having a scan data input (SDI) and a scan data output (SDO) comprising: a plurality of predefined shift register latches (SRLs) of said scan ring for storing a unique predetermined identification number included in each LSI chip to be identified; said plurality of predefined shift register latches being located a predetermined number N of pad SRLs from said scan data output SDO; and means for selectively reading out said stored predetermined identification number to identify the LSI chip.

Claim 9

Apparatus for uniquely identifying large scale integrated (LSI) circuit chips of the type conforming to scan design systems and testing techniques and having a plurality of shift register latches storage elements forming a scan ring having a scan data input (SDI) and a scan data output (SDO) comprising: a plurality of predefined shift register latches (SRLs) of said scan ring for storing a unique predetermined identification number included in each LSI chip to be identified; said plurality of predefined shift register latches being located a predetermined number N of pad SRLs from said scan data output SDO; and means for selectively reading out said stored predetermined identification number to identify the LSI chip.

Claim 10

Apparatus as recited in claim 7 wherein said predetermined number N of pad SRLs is a selected integer greater than or equal to zero.

Claim 11

Apparatus as recited in claim 7 wherein each of said plurality of predefined shift register latches includes a functional data input D further comprising: means coupled to said functional data input D for providing a selected signal, said selected signal being either a logical one or a logical zero.

Claim 12

Apparatus as recited in claim 7 wherein said means for selectively reading out said stored predetermined identification number to identify the LSI chip include: means for detecting a predetermined number N of bit-shifts; said detected predetermined number N of bit-shifts corresponding to a predetermined number N of pad SRLs from said SDO, and means for identifying said stored predetermined identification number responsive to said detected number N bit-shifts.

Claim 13

Apparatus as recited in claim 7 wherein said plurality of predefined shift register latches store a first predetermined number L of bits for defining a chip ID number and a second predetermined number M of bits for defining a chip level ID number.

Claim 16

A method as recited in claim 12 wherein said step of selectively reading out said stored predetermined identification number to identify the LSI chip includes the steps of: detecting N bit-shifts corresponding to said predetermined number N of pad SRLs; and identifying said stored predetermined identification number responsive to said detected N bit-shifts.