Patent US5079692A successfully refreshed from Google Patents.
US5079692A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Controller which allows direct access by processor to peripheral units
Assignee: Hitachi Ltd
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Filing: 1989-08-25
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Granted: 1992-01-07
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Expires: 2009-08-25
Abstract
Abstract A controller such as a CRT controller is connected to a microprocessor via a system bus and has connecting terminals for its peripheral units. This controller is provided with a control terminal for receiving the control signal supplied from the microprocessor and control means for providing high impedance at the connecting terminal in response to the control signal. The controller having such a construction permits the microprocessor to directly access the peripheral units.
Inventors
- 👤 Hiroshi Takeda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 22:02
CPC Classifications
G; G06; G06F; G06F12/00; G06F13/00; G06F13/38; G06F13/42; G06F13/4204; G06F13/4221; G06F13/4226
Claims Analysis
Total Claims: 31
Claim 1
Independent Claim
207 words
A system comprising: a microprocessor; first memory means for storing information; a first bus coupled to said microprocessor and to said first memory means; a second bus; second memory means coupled to said second bus for storing information; a controller integrated circuit device couple to said first bus and to said second bus for accessing said second memory means via said second bus, said controller integrated circuit device including a first external terminal coupled to said microprocessor, a second external terminal coupled to said microprocessor, release means coupled to said microprocessor for releasing said second bus from said controller integrated circuit device in response to a first control signal supplied by said microprocessor to said first external terminal and signal generating means for generating a second control signal to be supplied to said microprocessor via said second external terminal in response to the release of said second bus from said controller integrated circuit device; and transfer means coupled between said first bus and said second bus and coupled to said second external terminal, for enabling a signal on said first bus to be transferred to said second bus in response to said second control signal supplied via said second external terminal of said controller integrated circuit device.
Claim 2
Independent Claim
207 words
A system comprising: a microprocessor; first memory means for storing information; a first bus coupled to said microprocessor and to said first memory means; a second bus; second memory means coupled to said second bus for storing information; a controller integrated circuit device couple to said first bus and to said second bus for accessing said second memory means via said second bus, said controller integrated circuit device including a first external terminal coupled to said microprocessor, a second external terminal coupled to said microprocessor, release means coupled to said microprocessor for releasing said second bus from said controller integrated circuit device in response to a first control signal supplied by said microprocessor to said first external terminal and signal generating means for generating a second control signal to be supplied to said microprocessor via said second external terminal in response to the release of said second bus from said controller integrated circuit device; and transfer means coupled between said first bus and said second bus and coupled to said second external terminal, for enabling a signal on said first bus to be transferred to said second bus in response to said second control signal supplied via said second external terminal of said controller integrated circuit device.
Claim 3
Dependent Claim
68 words
A system according to claim 1, wherein said first bus includes a first address bus and a first data bus, and said second bus includes a second address bus and a second data bus; and said transfer means includes address transfer means coupled between said first address bus and said second address bus, and data transfer means coupled between said first data bus and said second data bus.
Claim 4
Dependent Claim
70 words
A system according to claim 2, wherein said address transfer means includes means for enabling an address signal on said first address bus to be transferred to said second address bus in response to said second control signal; and said data transfer means includes means for enabling a data signal on said first data bus to be transferred to said second data bus in response to said second control signal.
Claim 5
Independent Claim
217 words
A system comprising: a microprocessor; first memory means for storing information; a first bus coupled to said microprocessor and to said first memory means; a second bus; second memory means coupled to said second bus for storing information; a controller integrated circuit device coupled to said first bus and to said second bus and responsive to a command supplied via said first bus for supplying data to said second memory means via said second bus, said controller integrated circuit device including a first external terminal coupled to said microprocessor, a second external terminal coupled to said microprocessor, release means coupled to said microprocessor for releasing said second bus from said controller integrated circuit device in response to a first control signal supplied by said microprocessor to said first external terminal, and generating means for generating a second control signal to be supplied to said microprocessor via said second external terminal in response to the release of said second bus from said controller integrated circuit device; and transfer means coupled between said first bus and said second but and to said second external terminal for enabling a signal on said first bus to be transferred to said second bus in response to said second control signal provided by said second external terminal of said controller integrated circuit device.
Claim 6
Independent Claim
217 words
A system comprising: a microprocessor; first memory means for storing information; a first bus coupled to said microprocessor and to said first memory means; a second bus; second memory means coupled to said second bus for storing information; a controller integrated circuit device coupled to said first bus and to said second bus and responsive to a command supplied via said first bus for supplying data to said second memory means via said second bus, said controller integrated circuit device including a first external terminal coupled to said microprocessor, a second external terminal coupled to said microprocessor, release means coupled to said microprocessor for releasing said second bus from said controller integrated circuit device in response to a first control signal supplied by said microprocessor to said first external terminal, and generating means for generating a second control signal to be supplied to said microprocessor via said second external terminal in response to the release of said second bus from said controller integrated circuit device; and transfer means coupled between said first bus and said second but and to said second external terminal for enabling a signal on said first bus to be transferred to said second bus in response to said second control signal provided by said second external terminal of said controller integrated circuit device.
Claim 7
Dependent Claim
58 words
A system according to claim 4, wherein said controller integrated circuit device includes third memory means for temporarily storing a plurality of commands supplied via said first bus, and means coupled to said third memory means for forming data to be transferred to said second memory means in accordance with a command provided from said third memory means.
Claim 8
Dependent Claim
135 words
A system according to claim 5, wherein said first bus includes a first address bus, and a first data bus which transfers said command to said controller integrated circuit device; said second bus includes a second address bus, and a second data bus which transfers data to said second memory means; and said transfer means includes address transfer means coupled between said first address bus and said second address bus for enabling an address signal on said first address bus to be transferred to said second address bus in response to said second control signal, and data transfer means coupled between said first data bus and said second data bus for enabling a data signal on said first data bus to be transferred to said second data bus in response to said second control signal.
Claim 9
Independent Claim
217 words
A system comprising: a microprocessor; first memory means for storing information; a first bus coupled to said microprocessor and to said first memory means; a second bus; drawing memory means coupled to said second bus for storing data; a CRT controller integrated circuit device coupled to said first bus and to said second bus for providing data, formed by processing a drawing command supplied via said first bus, to said drawing memory means via said second bus, said CRT controller integrated circuit device including a first external terminal coupled to said microprocessor, a second external terminal coupled to said microprocessor, release means coupled to said microprocessor for releasing said second bus from said CRT controller integrated circuit device in response to a request control signal supplied by said microprocessor to said first external terminal and generating means for generating an acknowledge control signal to be supplied to said microprocessor via said second external terminal in response to the release of said second bus from said CRT controller integrated circuit device; and transfer means coupled between said first bus and said second bus and coupled to said second external terminal for enabling a signal on said first bus to be transferred to said second bus in response to said acknowledge control signal supplied via said second external terminal.
Claim 10
Independent Claim
217 words
A system comprising: a microprocessor; first memory means for storing information; a first bus coupled to said microprocessor and to said first memory means; a second bus; drawing memory means coupled to said second bus for storing data; a CRT controller integrated circuit device coupled to said first bus and to said second bus for providing data, formed by processing a drawing command supplied via said first bus, to said drawing memory means via said second bus, said CRT controller integrated circuit device including a first external terminal coupled to said microprocessor, a second external terminal coupled to said microprocessor, release means coupled to said microprocessor for releasing said second bus from said CRT controller integrated circuit device in response to a request control signal supplied by said microprocessor to said first external terminal and generating means for generating an acknowledge control signal to be supplied to said microprocessor via said second external terminal in response to the release of said second bus from said CRT controller integrated circuit device; and transfer means coupled between said first bus and said second bus and coupled to said second external terminal for enabling a signal on said first bus to be transferred to said second bus in response to said acknowledge control signal supplied via said second external terminal.
Claim 11
Dependent Claim
60 words
A system according to claim 7, wherein said CRT controller integrated circuit device includes drawing memory means for temporarily storing a plurality of drawing commands supplied via said first bus, and means coupled to said drawing memory means for forming data to be transferred to said second memory means by processing a drawing command provided from said drawing memory means.
Claim 12
Dependent Claim
138 words
A system according to claim 8, wherein said first bus includes a first address bus, and a first data bus which transfers said drawing command to said CRT controller integrated circuit device; said second bus includes a second address bus, and a second data bus which transfers data to said drawing memory means; and said transfer means includes a address transfer means coupled between said first address bus and said second address bus for enabling an address signal on said first address bus to be transferred to said second address bus in response to said acknowledge control signal, and data transfer means coupled between said first data bus and said second data bus for enabling a data signal on said first data bus to be transferred to said second data bus in response to said acknowledge control signal.
Claim 13
Dependent Claim
33 words
A system according to claim 9, further comprising video signal forming means coupled to said second data bus for forming a video signal according to a data stored in said drawing memory means.
Claim 14
Dependent Claim
32 words
A system according to claim 7, further comprising video signal forming means coupled to said drawing memory means for forming a video signal according to data stored in said drawing memory means.
Claim 15
Dependent Claim
18 words
A system according to claim 11, wherein said video signal forming means is coupled to said second bus.
Claim 16
Independent Claim
229 words
A system comprising: a microprocessor; first memory means for storing information; a first bus coupled to said microprocessor and to said first memory means; a second bus; drawing memory means coupled to said second bus for storing data; a CRT controller integrated circuit device coupled to said first bus and to said second bus for providing data, formed by processing a drawing command applied via said first bus, to said drawing memory means via said second bus, said CRT controller integrated circuit device including a first external terminal coupled to said microprocessor, a second external terminal coupled to said microprocessor, first means coupled to said microprocessor for releasing said second bus from said CRT controller integrated circuit device in response to a request control signal supplied by said microprocessor to said first external terminal and second means coupled to said first means for generating an acknowledge control signal for indicating the release of said second bus from said CRT controller means said acknowledge control signal being supplied to said microprocessor via said second external terminal; and transfer means coupled between said first bus and said second bus and coupled to said second external terminal for enabling a signal on said first bus to be transferred to said second bus in response to said acknowledge control signal supplied by said CRT controller integrated circuit device via said second external terminal.
Claim 17
Independent Claim
229 words
A system comprising: a microprocessor; first memory means for storing information; a first bus coupled to said microprocessor and to said first memory means; a second bus; drawing memory means coupled to said second bus for storing data; a CRT controller integrated circuit device coupled to said first bus and to said second bus for providing data, formed by processing a drawing command applied via said first bus, to said drawing memory means via said second bus, said CRT controller integrated circuit device including a first external terminal coupled to said microprocessor, a second external terminal coupled to said microprocessor, first means coupled to said microprocessor for releasing said second bus from said CRT controller integrated circuit device in response to a request control signal supplied by said microprocessor to said first external terminal and second means coupled to said first means for generating an acknowledge control signal for indicating the release of said second bus from said CRT controller means said acknowledge control signal being supplied to said microprocessor via said second external terminal; and transfer means coupled between said first bus and said second bus and coupled to said second external terminal for enabling a signal on said first bus to be transferred to said second bus in response to said acknowledge control signal supplied by said CRT controller integrated circuit device via said second external terminal.
Claim 18
Dependent Claim
60 words
A system according to claim 13, wherein said CRT controller integrated circuit device includes third memory means for temporarily storing a plurality of drawing commands supplied via said first bus, and means coupled to said drawing memory means for forming data to be transferred to said drawing memory means by processing a drawing command provided from said third memory means.
Claim 19
Dependent Claim
138 words
A system according to claim 14, wherein said first bus includes a first address bus, and a first data bus which transfers said drawing commands to said CRT controller integrated circuit device; said second bus includes a second address bus, and a second data bus which transfers data to said drawing memory means; and said transfer means includes an address transfer means coupled between said first address bus and said second address bus for enabling in address signal on said first address bus to be transferred to said second address bus in response to said acknowledge control signal, and data transfer means coupled between said first data bus and said second data bus for enabling a data signal on said first data bus to be transferred to said second data bus in response to said acknowledge control signal.
Claim 20
Dependent Claim
33 words
A system according to claim 15, further comprising video signal forming means coupled to said second data bus for forming a video signal according to a data stored in said drawing memory means.
Claim 21
Dependent Claim
32 words
A system according to claim 13, further comprising video signal forming means coupled to said drawing memory means for forming a video signal according to data stored in said drawing memory means.
Claim 22
Dependent Claim
18 words
A system according to claim 17, wherein said video signal forming means is coupled to said second bus.
Claim 23
Independent Claim
246 words
A system comprising: a microprocessor; first memory means for storing information; a first bus coupled to said microprocessor and to said first memory means; a second bus; drawing memory means coupled to said second bus for storing data; a CRT controller integrated circuit device coupled to said first bus and to said second bus for providing data, formed by processing a drawing command applied via said first bus, to said drawing memory means via said second bus, said CRT controller integrated circuit device including a first external terminal coupled to said microprocessor, a second external terminal coupled to said microprocessor, first means coupled to said microprocessor for releasing said second bus from said CRT controller integrated circuit device in response to a request control signal supplied by said microprocessor to said first external terminal, second means responsive to said request control signal for stopping the operation of an internal control section, and third means coupled to said first means for generating an acknowledge control signal for indicating the release of said second bus from said CRT controller means said acknowledge control signal being supplied to said microprocessor via said second external terminal; and transfer means coupled between said first bus and said second bus and coupled to said second external terminal for enabling a signal on said first bus to be transferred to said second bus in response to said acknowledge control signal supplied by said CRT controller integrated circuit device via said second external terminal.
Claim 24
Independent Claim
246 words
A system comprising: a microprocessor; first memory means for storing information; a first bus coupled to said microprocessor and to said first memory means; a second bus; drawing memory means coupled to said second bus for storing data; a CRT controller integrated circuit device coupled to said first bus and to said second bus for providing data, formed by processing a drawing command applied via said first bus, to said drawing memory means via said second bus, said CRT controller integrated circuit device including a first external terminal coupled to said microprocessor, a second external terminal coupled to said microprocessor, first means coupled to said microprocessor for releasing said second bus from said CRT controller integrated circuit device in response to a request control signal supplied by said microprocessor to said first external terminal, second means responsive to said request control signal for stopping the operation of an internal control section, and third means coupled to said first means for generating an acknowledge control signal for indicating the release of said second bus from said CRT controller means said acknowledge control signal being supplied to said microprocessor via said second external terminal; and transfer means coupled between said first bus and said second bus and coupled to said second external terminal for enabling a signal on said first bus to be transferred to said second bus in response to said acknowledge control signal supplied by said CRT controller integrated circuit device via said second external terminal.
Claim 25
Dependent Claim
60 words
A system according to claim 19, wherein said CRT controller integrated circuit device includes third memory means for temporarily storing a plurality of drawing commands supplied via said first bus, and means coupled to said drawing memory means for forming data to be transferred to said drawing memory means by processing a drawing command provided from said third memory means.
Claim 26
Dependent Claim
138 words
A system according to claim 20, wherein said first bus includes a first address bus, and a first data bus which transfers said drawing commands to said CRT controller integrated circuit device; said second bus includes a second address bus, and a second data bus which transfers data to said drawing memory means; and said transfer means includes an address transfer means coupled between said first address bus and said second address bus for enabling an address signal on said first address bus to be transferred to said second address bus in response to said acknowledge control signal, and data transfer means coupled between said first data bus and said second data bus for enabling a data signal on said first data bus to be transferred to said second data bus in response to said acknowledge control signal.
Claim 27
Dependent Claim
32 words
A system according to claim 21, further comprising video signal forming means coupled to said second data bus for forming a video signal according to data stored in said drawing memory means.
Claim 28
Dependent Claim
32 words
A system according to claim 19, further comprising video signal forming means coupled to said drawing memory means for forming a video signal according to data stored in said drawing memory means.
Claim 29
Dependent Claim
18 words
A system according to claim 23, wherein said video signal forming means is coupled to said second bus.
Claim 30
Independent Claim
224 words
A system comprising: a microprocessor; first memory means for storing information; a first bus coupled to said microprocessor and to said first memory means; a second bus; second memory means coupled to said second bus for storing information; a controller integrated circuit device coupled to said first bus and to said second bus for accessing said second memory means via said second bus, said controller integrated circuit device including a first external terminal coupled to said microprocessor, a second external terminal coupled to said microprocessor, release means coupled to said microprocessor for releasing said second bus from said controller integrated circuit device in response to a first control signal supplied by said microprocessor to said first external terminal, means responsive to said first control signal for stopping the operation of an internal control section, and signal generating means for generating a second control signal for indicating the release of said second bus from said controller integrated circuit device, said second control signal supplied to said microprocessor via said second external terminal; and transfer means coupled between said first bus and said second bus and coupled to said second external terminal, for enabling a signal on said first bus to be transferred to said second bus in response to said second control signal supplied via said second external terminal of said controller integrated circuit device.
Claim 31
Independent Claim
224 words
A system comprising: a microprocessor; first memory means for storing information; a first bus coupled to said microprocessor and to said first memory means; a second bus; second memory means coupled to said second bus for storing information; a controller integrated circuit device coupled to said first bus and to said second bus for accessing said second memory means via said second bus, said controller integrated circuit device including a first external terminal coupled to said microprocessor, a second external terminal coupled to said microprocessor, release means coupled to said microprocessor for releasing said second bus from said controller integrated circuit device in response to a first control signal supplied by said microprocessor to said first external terminal, means responsive to said first control signal for stopping the operation of an internal control section, and signal generating means for generating a second control signal for indicating the release of said second bus from said controller integrated circuit device, said second control signal supplied to said microprocessor via said second external terminal; and transfer means coupled between said first bus and said second bus and coupled to said second external terminal, for enabling a signal on said first bus to be transferred to said second bus in response to said second control signal supplied via said second external terminal of said controller integrated circuit device.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-01-06 | 1995-07-08 | 1996-01-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-01-06 | 1999-07-08 | 2000-01-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-01-06 | 2003-07-08 | 2004-01-07 | $7700.00 | Window Closed / Lapsed |