US5079604A
Expired / Lapsed
US
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SOI layout for low resistance gate
Assignee: Texas Instruments Inc
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Filing: 1991-05-29
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Granted: 1992-01-07
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Expires: 2011-05-29
Abstract
Abstract Silicon-on-insulator mesa steps cause high resistance in polycrystalline material because of the lack of silicide coverage. In a gate or word line, for instance, this accounts for a large resistance. By connecting the mesas through the body nodes of adjacent transistors, all mesa steps in a polycrystalline semiconductor gate are eliminated. Thus, gate or word line resistance is reduced.
Inventors
- 👤 Theodore W. Houston
- 👤 Terence G. W. Blake
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 23:52
CPC Classifications
H; H10; H10D; H10D86/00; H10D86/201
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
82 words
A transistor structure comprising: a commonly gated first transistor and second transistor, said transistors being formed in a thin film of semiconductor material overlying an insulator, said thin film being patterned to form a mesa for each transistor, and an extension of semiconductor material from the body node of said first transistor to the body node of said second transistor so as to form a substantially planar surface of mesa, flush with an edge abutting said common gate, underlying the common gate.
Claim 2
Dependent Claim
82 words
A transistor structure comprising: a commonly gated first transistor and second transistor, said transistors being formed in a thin film of semiconductor material overlying an insulator, said thin film being patterned to form a mesa for each transistor, and an extension of semiconductor material from the body node of said first transistor to the body node of said second transistor so as to form a substantially planar surface of mesa, flush with an edge abutting said common gate, underlying the common gate.
Claim 3
Dependent Claim
16 words
A transistor structure as recited in claim 1 which further comprises isolation tabs between said mesas.
Claim 4
Dependent Claim
20 words
A transistor structure as recited in claim 2 wherein said isolation tabs comprise semiconductor material flanked with a sidewall insulator.
Claim 5
Dependent Claim
14 words
A transistor structure as recited in claim 3 wherein said sidewall insulator is oxide.
Claim 6
Dependent Claim
40 words
A transistor structure as recited in claim 1 wherein parasitic current is reduced by implanting dopants into the mesa between said transistors so as to raise the threshold voltage of a parasitic transistor formed between said first and second transistors.
Claim 7
Dependent Claim
22 words
A transistor structure as recited in claim 1 wherein a body node contact is made to the mesa extension between two transistors.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-01-06 | 1995-07-08 | 1996-01-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-01-06 | 1999-07-08 | 2000-01-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-01-06 | 2003-07-08 | 2004-01-07 | $7700.00 | Window Closed / Lapsed |