Patent US5077677A successfully refreshed from Google Patents.
US5077677A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Probabilistic inference gate
Assignee: Micron Technology Inc
•
Filing: 1989-06-12
•
Granted: 1991-12-31
•
Expires: 2009-06-12
Abstract
Abstract The present system performs linear transformations on input probabilities and produces outputs which indicate the likelihood of one or more events. The transformation performed is a product of linear transforms such as Po=[AjPj+Bj]x[AkPk+Bk] where Pj and Pk are input probabilities, Po is an output event probability and Aj, Bj, Ak and Bk are transformation constants. The system includes a basic processing unit or computational unit which performs a probabilistic gate operation to convert two input probability signals into one output probability signal where the output probability is equal to the product of linear transformations of the input probabilities. By appropriate selection of transformation constants logical and probabilistic gates performing the functions of AND, NAND, OR, NOR, XOR, NOT, IMPLIES and NOT IMPLIES can be created. The basic unit can include three multipliers and two adders if a discrete component hardwired version is needed for speed or a single multiplier/adder, associated storage and multiplex circuits can be used to accomplish the functions of the hardwired version for economy. This basic unit can also be provided as a software implementation, can be implemented as a hardwired decision tree element implementation or implemented as a universal probabilistic processor and provided with a bus communication structure to create expert systems or neural networks suitable for specific tasks. The basic units can be combined to produce a virtual basic building block which has more virtual processors than physical processors to improve processor utilization. The building blocks can be combined into an array to produce either a high speed expert system or a high speed neural network.
Inventors
- 👤 John H. Murphy
- 👤 Terry A. Jeeves
- 👤 Arthur A. Anderson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 17:11
CPC Classifications
G; G06; G06F; G06F7/00; G06N; G06N5/00; G06N5/01; G06N5/02; G06N5/022; G06N5/025; G06N5/04; G06N5/048; Y; Y10; Y10S; Y10S706/00; Y10S706/90
Claims Analysis
Total Claims: 35
Claim 1
Independent Claim
59 words
A processing element producing an inference, comprising: first and second input lines receiving first and second input signals; a digital universal inference gate connected to said first and second input lines, receiving the first and second input signals, for performing a digital linear transformation and combination of the first and second input signals and producing an output probabilistic inference.
Claim 2
Dependent Claim
59 words
A processing element producing an inference, comprising: first and second input lines receiving first and second input signals; a digital universal inference gate connected to said first and second input lines, receiving the first and second input signals, for performing a digital linear transformation and combination of the first and second input signals and producing an output probabilistic inference.
Claim 3
Dependent Claim
59 words
An element as recited in claim 1, wherein said gate digitally executes P o =A j P j +B j ]·[A k P k +B k ] where P o is an output probability of P j and P k are input probability signals and A j , B j , A k and B k are transformation constants.
Claim 4
Dependent Claim
26 words
An element as recited in claim 1, wherein said first and second input signals are digital probability input signals and said output inference is a probability.
Claim 5
Dependent Claim
22 words
An element as recited in claim 1, wherein said gate digitally combines linear transformations of the input signals as the output inference.
Claim 6
Dependent Claim
23 words
An element as recited in claim 1, wherein the output is fed back via a digital bus as one of the input signals.
Claim 7
Dependent Claim
61 words
An element as recited in claim 1, wherein said gate digitally executes P o =[A j P j +B j ]·[A k P k +B k ]+C m where P o is the output probability, P j and P k are input probabilities and A j , B j , A k , B k and C m are transformation constants.
Claim 8
Dependent Claim
76 words
An element as recited in claim 1, wherein said gate comprises: first digital linear transformation means for performing a first digital linear transformation on the first input signal using first and second constants; second digital linear transformation means for performing a second digital linear transformation on the second input signal using third and fourth constants; and combination means for digitally combining the first and second digital linear transformations producing an output probability as the output inference.
Claim 9
Dependent Claim
63 words
An element as recited in claim 7, wherein said first digital linear transformation means comprises: a first multiplier; and a first adder connected to said first multiplier; wherein said second digital linear transformation means comprises: a second multiplier; and a second adder connected to said second multiplier; and wherein said combination means comprises a third multiplier connected to said first and second adders.
Claim 10
Dependent Claim
143 words
An element as recited in claim 7, wherein said first digital linear transformation means comprises: a first digital multiplier circuit digitally multiplying the first input signal times the first constant producing a first output; and a first digital adder circuit, connected to said first multiplier circuit, digitally adding the second constant to the first output producing a second output; wherein said second digital linear transformation means comprises: a second digital multiplier circuit digitally multiplying the second input signal times the third constant producing a third output; and a second digital adder circuit, connected to said second multiplier, digitally adding the fourth constant to the third output producing a fourth output; and wherein said combination means comprises a third digital multiplier circuit, connected to said first and second digital adder circuits, digitally multiplying the second output times the fourth output producing the output probability.
Claim 11
Dependent Claim
59 words
An element as recited in claim 1, wherein said gate comprises: first and second universal digital implication elements each performing a digital linear transformation and producing first and second implication outputs from said first and second input signals, respectively; and first digital combining means for digitally combining the first and second implication outputs to produce a first output inference.
Claim 12
Dependent Claim
87 words
An element as recited in claim 10, wherein said universal gate further receives third and fourth input signals and said gate further comprises: third and fourth universal digital implication elements producing third and fourth implication outputs from said third and fourth input signals, respectively; second digital combining means for digitally combining the third and fourth implication outputs to produce a second output inference; and third digital combining means for digitally combining the first and second output inferences to produce a third output inference as the output inference.
Claim 13
Dependent Claim
59 words
An element as recited in claim 11, wherein said first through fourth universal digital implication elements each perform digital linear transformations on the first through fourth input signals, said first and second combining means digitally multiplies the first and second implications and second and third implications respectively and said third combining means digitally multiplies the first and second inferences.
Claim 14
Dependent Claim
63 words
An element as recited in claim 1, wherein said digital universal inference gate comprises: a latch register storing the first and second input signals; and a digital computation unit, connected to said latch register, and performing digital linear transformations on the first and second input signals using constants and digitally combining the linear transformations producing a first output probability as the output inference.
Claim 15
Dependent Claim
129 words
A processing element producing an inference, comprising: a universal inference gate receiving first and second input signals and producing an output inference, said universal inference gate comprising: a latch storing the first and second input signals; and a computation unit, connected to said latch, and performing linear transformations on the first and second input signals using constants and combining the linear transformations producing a first output probability, said computation unit comprising a multiplier/adder and said element further comprises: storage means for storing the constants; a timing control circuit connected to said multiplier/adder and said storage means, and producing selection and timing signals; and a first multiplexer, connected to said storage means, said timing control circuit, said latch and said multiplier/adder for selecting one of the input signals and constants.
Claim 16
Dependent Claim
129 words
A processing element producing an inference, comprising: a universal inference gate receiving first and second input signals and producing an output inference, said universal inference gate comprising: a latch storing the first and second input signals; and a computation unit, connected to said latch, and performing linear transformations on the first and second input signals using constants and combining the linear transformations producing a first output probability, said computation unit comprising a multiplier/adder and said element further comprises: storage means for storing the constants; a timing control circuit connected to said multiplier/adder and said storage means, and producing selection and timing signals; and a first multiplexer, connected to said storage means, said timing control circuit, said latch and said multiplier/adder for selecting one of the input signals and constants.
Claim 17
Dependent Claim
32 words
An element as recited in claim 14, further comprising: a second multiplexer, connected to receive the first and second input signals and third and fourth input signals, and connected to said latch.
Claim 18
Dependent Claim
45 words
A processing element producing an implication, comprising: an input line receiving an input signal; and a digital universal implication gate connected to said input line, receiving the input signal, for performing a digital linear transformation on the input signal and producing a probabilistic implication output.
Claim 19
Dependent Claim
45 words
A processing element producing an implication, comprising: an input line receiving an input signal; and a digital universal implication gate connected to said input line, receiving the input signal, for performing a digital linear transformation on the input signal and producing a probabilistic implication output.
Claim 20
Dependent Claim
40 words
An element as recited in claim 16, wherein said gate digitally executes P.sub.o =A.sub.j P.sub.j +B.sub.j to produce the implication output P o , where A j and B j are transformation constants and P j is the input signal.
Claim 21
Dependent Claim
35 words
An element as recited in claim 16, wherein said gate digitally executes ##EQU9## to produce the implication output P o where A j and B j are transformation constants and P j is input signals.
Claim 22
Dependent Claim
18 words
An element as recited in claim 16, wherein the implication output is fed back as an intermediate implication.
Claim 23
Dependent Claim
57 words
An element as recited in claim 16, wherein said gate digitally executes: P.sub.o =[A.sub.i-1 P.sub.i-1 +B.sub.31 1 ]·[A.sub.i P.sub.i +B.sub.i ] to produce a probabilistic inference P o where A i , B i , A i-1 and B i-1 are transformation constants and P i is a current input and P i-1 is a previous input.
Claim 24
Independent Claim
61 words
A method of performing an inference operation, comprising the steps of: (a) performing a first digital linear transformation on a first input signal using a digital computer; (b) performing a second digital linear transformation on a second input signal using a digital computer; and (c) combining the first and second linear transformations using a digital computer to produce a probabilistic inference.
Claim 25
Independent Claim
61 words
A method of performing an inference operation, comprising the steps of: (a) performing a first digital linear transformation on a first input signal using a digital computer; (b) performing a second digital linear transformation on a second input signal using a digital computer; and (c) combining the first and second linear transformations using a digital computer to produce a probabilistic inference.
Claim 26
Dependent Claim
22 words
A method as recited in claim 21, wherein step (c) comprises digitally multiplying the first linear transformation by the second linear transformation.
Claim 27
Dependent Claim
19 words
A method as recited in claim 21, wherein said first and second input signals and said inference are probabilities.
Claim 28
Independent Claim
27 words
A method of performing an implication operation, comprising: (a) performing a digital linear transformation on an input signal using a digital computer to produce a probabilistic implication.
Claim 29
Independent Claim
27 words
A method of performing an implication operation, comprising: (a) performing a digital linear transformation on an input signal using a digital computer to produce a probabilistic implication.
Claim 30
Dependent Claim
44 words
A method as recited in claim 24, wherein step (a) digitally performs P o =A j P j +B j to produce a probability implication P o where A j and B j are transformation constants and P j is a probability input signal.
Claim 31
Dependent Claim
113 words
A weighted decision gate receiving first through fourth input signals, said gate comprising: a first digital multiplier circuit digitally multiplying the first and second input signals; a second digital multiplier circuit digitally multiplying the third and fourth input signals; a first digital universal gate receiving the output of the first digital multiplier circuit and the second input signal, and for digitally producing a probabilistic inference of a parameter; a second universal gate receiving the output of the second digital multiplier circuit and the fourth input signal, performing a linear transformation and producing a digital parameter probability; and a digital divider circuit digitally dividing the probabilistic inference by the probability to produce the parameter.
Claim 32
Dependent Claim
113 words
A weighted decision gate receiving first through fourth input signals, said gate comprising: a first digital multiplier circuit digitally multiplying the first and second input signals; a second digital multiplier circuit digitally multiplying the third and fourth input signals; a first digital universal gate receiving the output of the first digital multiplier circuit and the second input signal, and for digitally producing a probabilistic inference of a parameter; a second universal gate receiving the output of the second digital multiplier circuit and the fourth input signal, performing a linear transformation and producing a digital parameter probability; and a digital divider circuit digitally dividing the probabilistic inference by the probability to produce the parameter.
Claim 33
Independent Claim
101 words
A system, comprising: a first digital probabilistic gate receiving first and second input signals, for performing a digital linear transformation on and combination of said first and second input signals and producing a first probabilistic inference; a second digital probabilistic gate receiving third and fourth input signals, for performing a digital linear transformation and combination of said third and fourth input signals and producing a second probabilistic inference; and a third probabilistic gate connected to said first and second probabilistic gates, for performing a digital linear transformation and combination of the first and second inferences and producing a third probabilistic inference.
Claim 34
Independent Claim
101 words
A system, comprising: a first digital probabilistic gate receiving first and second input signals, for performing a digital linear transformation on and combination of said first and second input signals and producing a first probabilistic inference; a second digital probabilistic gate receiving third and fourth input signals, for performing a digital linear transformation and combination of said third and fourth input signals and producing a second probabilistic inference; and a third probabilistic gate connected to said first and second probabilistic gates, for performing a digital linear transformation and combination of the first and second inferences and producing a third probabilistic inference.
Claim 35
Dependent Claim
24 words
A system as recited in claim 27, wherein said first, second and third inferences and said first and second input signals are digital probabilities.
References Cited (Backward Citations)
US3259735A
Cited
US3803390A
Cited
US3757261A
Cited
US4620188A
Cited
US4594678A
Cited
US4611305A
Cited
US4593367A
Cited
US4620286A
Cited
US4599692A
Cited
US4694418A
Cited
US4641356A
Cited
US4875184A
Cited
US4945506A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-12-30 | 1995-07-01 | 1995-12-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-12-30 | 1999-07-01 | 1999-12-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-12-30 | 2003-07-01 | 2003-12-31 | $7700.00 | Window Closed / Lapsed |