US4620188A
Expired / Lapsed
US
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Multi-level logic circuit
Assignee: Development Finance Corp of New Zealand
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Filing: 1982-08-13
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Granted: 1986-10-28
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Expires: 2002-08-13
Abstract
Abstract A Multi-Level Logic Circuit is described, with the hardware of the circuit capable of being constructed to operate in a chosen base. The circuit includes at least: (a) One input level detector which can receive one or more multi-level inputs, (b) Control switching means, and (c) An output level generator delivering a single multi-level output. Various logic gates operating in any base can be derived from the generalized circuit of this invention. Basic multi-level logic gates include an (n-1) complementer, where an output of (n-1-a) is generated from a discrete input "a" where n is the base for which the circuit is constructed. A complementary maximum gate is also described in which the circuit provides the (n-1) complement of the highest logic level detected on input lines to the input level detector. Various other multi-level logic circuits can be constructed by combining the multi-level complementer, and multi-level complementary maximum gates. Circuits are also described where there are more than one input level detector or control switching means to provide binary operations on inputs to the multi-level logic circuits, e.g. addition, multiplication, in any desired base. Circuits are illustrated, constructed to operate in base 10. The multi-level logic circuit is similar to a binary circuit in that it operates on discrete logic levels. It is not an analog circuit.
Inventors
- 👤 Chanty Sengchanh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 21:42
CPC Classifications
G; G06; G06N; G06N7/00; G06N7/02; G06N7/04; G06N7/043; H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/082; H03K19/0823
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
309 words
A multi-level logic circuit operating in a base n where n is greater than 2, comprising (a) first logic circuit means including (1) a first input level detector having one multi-level detector for detecting any one of n logic levels and for producing a first output signal in response to an appropriate input logic level; (2) a first control switching device connected with said first input level detector for producing a first select signal in response to the output signal from said first level detector; and (3) a first output level generator connected with said first control switching device for producing in response to said first selected signal an output of logic level (n-1-a), wherein a is the input logic level detected by said first input level detector; and (b) second logic circuit means including (1) a second input level detector having a plurality of multi-level input lines arranged so that the highest logic level on one of said input lines is transmitted to the second input level detector which produces a second output signal in response to the highest logic level; (2) a second control switching device connected with said second input level detector for producing a second selected signal in response to said second output signal; and (3) a second output level generator connected with said second control switching device for producing in response to said second select signal an output of logic level (n-1-a x ), where a x is the highest logic level of the input logic levels (a 1 , a 2 , a 3 . . . a k ) detected by said second input level detector; said first and second input level detectors each including voltage dependent input switching means, respectively, and said first and second output level generators each including a voltage divider capable of providing n different voltage outputs, respectively.
Claim 2
Dependent Claim
309 words
A multi-level logic circuit operating in a base n where n is greater than 2, comprising (a) first logic circuit means including (1) a first input level detector having one multi-level detector for detecting any one of n logic levels and for producing a first output signal in response to an appropriate input logic level; (2) a first control switching device connected with said first input level detector for producing a first select signal in response to the output signal from said first level detector; and (3) a first output level generator connected with said first control switching device for producing in response to said first selected signal an output of logic level (n-1-a), wherein a is the input logic level detected by said first input level detector; and (b) second logic circuit means including (1) a second input level detector having a plurality of multi-level input lines arranged so that the highest logic level on one of said input lines is transmitted to the second input level detector which produces a second output signal in response to the highest logic level; (2) a second control switching device connected with said second input level detector for producing a second selected signal in response to said second output signal; and (3) a second output level generator connected with said second control switching device for producing in response to said second select signal an output of logic level (n-1-a x ), where a x is the highest logic level of the input logic levels (a 1 , a 2 , a 3 . . . a k ) detected by said second input level detector; said first and second input level detectors each including voltage dependent input switching means, respectively, and said first and second output level generators each including a voltage divider capable of providing n different voltage outputs, respectively.
Claim 3
Dependent Claim
42 words
Apparatus as defined in claim 1, wherein each control switching device includes (n-1) switching elements and each voltage divider comprises corresponding (n-1) logic units, each of which is capable of being by-passed by the associated switching element of said control switching device.
Claim 4
Dependent Claim
241 words
A multi-level logic circuit operating in a base n where n is greater than 2, comprising (a) a first input level detector for detecting a first input logic level and for producing a first output signal in response to an appropriate input logic level; (b) a second input level detector for detecting a second input logic level and for producing a second output signal n response to an appropriate input logic level; (c) control switching means connected with said first and second input level detectors for producing first and second select signals in response to the first and second output signals; and (d) output level generator means connected with said control switching means for producing a logic output in accordance with said first and second select signals, whereby a binary operation on said two input logic levels is performed resulting in a single multi-level output; said first and second input level detectors each comprising a one of n logic level recognizer having n outputs, respectively, the n outputs of a first logic level recognizer being used to switch a respective control switch which in turn by-passes a portion of said output level generator means, the n outputs of the second logic level recognizer being used to activate a further control switch connecting a supply to a particular point of the output level generator, whereby the combined operation of the two input level detectors enables said output operation on said two inputs.
Claim 5
Dependent Claim
241 words
A multi-level logic circuit operating in a base n where n is greater than 2, comprising (a) a first input level detector for detecting a first input logic level and for producing a first output signal in response to an appropriate input logic level; (b) a second input level detector for detecting a second input logic level and for producing a second output signal n response to an appropriate input logic level; (c) control switching means connected with said first and second input level detectors for producing first and second select signals in response to the first and second output signals; and (d) output level generator means connected with said control switching means for producing a logic output in accordance with said first and second select signals, whereby a binary operation on said two input logic levels is performed resulting in a single multi-level output; said first and second input level detectors each comprising a one of n logic level recognizer having n outputs, respectively, the n outputs of a first logic level recognizer being used to switch a respective control switch which in turn by-passes a portion of said output level generator means, the n outputs of the second logic level recognizer being used to activate a further control switch connecting a supply to a particular point of the output level generator, whereby the combined operation of the two input level detectors enables said output operation on said two inputs.
Claim 6
Dependent Claim
80 words
Apparatus as defined in claim 3, wherein said first and second input level detectors each comprise a one of n logic level recognizer having n outputs, respectively, the n outputs of a first logic level recognizer being connected to respective enabling switches capable of selecting a particular combined network of control switching means and said output level generator means, the n outputs of the second logic level recognizer being capable of controlling the control switching means of the selected network.
Claim 7
Dependent Claim
17 words
Apparatus as defined in claim 3, wherein each input level detector includes voltage dependent input switching means.
Claim 8
Dependent Claim
22 words
Apparatus as defined in claim 5, wherein said output level generator includes a voltage divider capable of providing n different voltage outputs.
Claim 9
Dependent Claim
18 words
Apparatus as defined in claim 5, wherein said output level generator includes a matrix of voltage level generators.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-10-27 | 1990-04-28 | 1990-10-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-10-27 | 1994-04-28 | 1994-10-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-10-27 | 1998-04-28 | 1998-10-28 | $7700.00 | Window Closed / Lapsed |