N-state logic circuit

Claim 2

An electronic circuit for generating an output signal having N discrete levels each representative of a different stable state where N > OR = 3, said circuit comprising: N bistable elements each having first and second terminals adapted to be coupled to first and second reference voltage sources and a control input terminal adapted to be coupled to an actuating signal; a plurality of unidirectional conducting devices for coupling together the first terminals of adjacent ones of said bistable elements, one of said first terminals serving as an output terminal for manifesting said N level output signal; and means for coupling said first terminal of individual ones of said bistable elements to the control input terminal of an adjacent one of said bistable elements so that actuation of one of said bistable elements by the application to the control input terminal thereof of an actuating signal maintains the control input terminal of the adjacent bistable element at a signal level sufficient to hold said adjacent bistable element in an non-actuated state, the remaining ones of said bistable elements being held in the non-actuated state by said unidirectional conducting devices.

Claim 3

The invention of claim 1 wherein said coupling means includes N voltage dividers each coupled between different ones of said bistable elements, each said voltage divider having one terminal thereof coupled to said first terminal of the associated bistable element, another terminal coupled to a third reference voltage source and an intermediate terminal coupled to the control input terminal of the adjacent one of said bistable elements.

Claim 4

The invention of claim 2 wherein each of said voltage dividers comprises a pair of resistors coupled in series, said intermediate terminal comprising the junction between said resistors.

Claim 5

The invention of claim 1 wherein said coupling means comprises a plurality of pairs of transistors, each pair of transistors having a first transistor with the base thereof coupled to the first terminal of a different one of said bistable elements, a second transistor having the base thereof coupled to an input terminal adapted to be coupled to a fourth reference voltage source, each said pair of transistors having common elements coupled together, the remaining terminal of said first transistor of each said pair being coupled to said first reference voltage, the remaining terminal of the other transistor of each said pair being coupled to the control input terminal of the adjacent bistable element.

Claim 6

An electronic counter comprising: a pair of logic elements, each logic element having a circuit operable in any one of N stable states representing a modulo N number system, each circuit including a plurality of operative stages, each stage adapted to be rendered operative when an input signal at a predetermined level is applied thereto, means responsive to means responsive to the actuation of one stage to the operative state by the application of an input signal thereto for applying an input signal at said predetermined level to an adjacent stage, whereby said adjacent stage is rendered and maintained operative, means responsive to the operation of a stage for maintaining the other stages inoperative, whereby each stage provides a respective stable operating state for a corresponding circuit, each stage of each circuit having a discrete potential with respect to the other stages of the circuit when a stage thereof is operative, the potentials of the stages of each circuit representing different counts of said number system, at least a first of said circuits having a signal output; and means responsive to a second input signal for alternately coupling one of the stages of said first circuit with a pair of stages of the second circuit, whereby one of said pair of adjacent stages of the second circuit will assume the potential of the stage of the first circuit and thereafter the stage of the first circuit will assume the potential of the other stage of said pair to thereby permit the output of the first circuit to represent counts of said number system.

Claim 7

An electronic counter comprising: a pair of logic elements, each logic element having a circuit operable in any one of N stable states representing a modulo N number system, each circuit including a plurality of operative stages, each stage adapted to be rendered operative when an input signal at a predetermined level is applied thereto, means responsive to means responsive to the actuation of one stage to the operative state by the application of an input signal thereto for applying an input signal at said predetermined level to an adjacent stage, whereby said adjacent stage is rendered and maintained operative, means responsive to the operation of a stage for maintaining the other stages inoperative, whereby each stage provides a respective stable operating state for a corresponding circuit, each stage of each circuit having a discrete potential with respect to the other stages of the circuit when a stage thereof is operative, the potentials of the stages of each circuit representing different counts of said number system, at least a first of said circuits having a signal output; and means responsive to a second input signal for alternately coupling one of the stages of said first circuit with a pair of stages of the second circuit, whereby one of said pair of adjacent stages of the second circuit will assume the potential of the stage of the first circuit and thereafter the stage of the first circuit will assume the potential of the other stage of said pair to thereby permit the output of the first circuit to represent counts of said number system.

Claim 8

An electronic counter as set forth in claim 5, wherein said coupling means includes an electronic gate.

Claim 9

An electronic counter as set forth in claim 5, wherein said coupling means includes a first electronic gate coupling said one stage of the first circuiT with one of said pair of stages of the second circuit, and a second gate coupling said one stage of the first circuit with the other of said pair of stages of the second circuit, the first gate being open when the second gate is closed and vice versa.

Claim 10

An electronic counter as set forth in claim 5, wherein each stage includes a transistor operating as an electronic switch to render the corresponding stage operative, said coupling means being operable to alternately connect the collector of the transistor of said one stage of the first circuit with the collectors of the transistors of said pair of stages of the second circuit.

Claim 11

An electronic counter as set forth in claim 5, wherein the potential of said one of said pair of stages is less than the potential of the other stage of said pair to thereby permit the output of the first circuit to provide a count up from a predetermined reference number.

Claim 12

An electronic counter as set forth in claim 5, wherein said one of said pair of stages of the first circuit has a potential greater than the other of said pair of stages to thereby permit the output of the first circuit to provide a count down from a predetermined reference number.