Method for manufacturing a trench capacitor of a one-transistor memory cell in a semiconductor substrate with a self-aligned capacitor plate electrode

Claim 2

Method for manufacturing a trench capacitor of a one-transistor memory cell in a semiconductor substrate, comprising the steps of: forming a trench overlapping with a field oxide that isolates various cells and forming a first capacitor electrode of the trench capacitor, manufacturing a first layer on a surface of the semiconductor substrate and on a surface of the first capacitor electrode; applying a second layer on the first layer and on the field oxide, and applying at least a third layer on the second layer and applying a leveling auxiliary layer on the at least third layer; removing the auxiliary layer at least until parts of at least the third layer are exposed, removing the exposed parts of the at least third layer at least until parts of the surface of the second layer are exposed; completely removing the auxiliary layer to produce a sacrificial layer at least on the exposed part of the surface of the second layer; completely removing the all remaining layers still situated on the surface of the second layer with the exception of the sacrificial layer, and structuring the second layer using the sacrificial layer as a mask to form a capacitor plate electrode of the trench capacitor.

Claim 3

Method according to claim 1, wherein one of a thermal or deposited silicon oxide is used as the first layer.

Claim 4

Method according to claim 1, wherein one of a double layer or a triple layer composed of silicon oxide and silicon nitride as constituents is used as the first layer.

Claim 5

Method according to claim 1, wherein a doped polycrystalline silicon layer is used as the second layer.

Claim 6

Method according to claim 1, wherein one of a thermal or deposited silicon oxide is used as the third layer.

Claim 7

Method according to claim 1, wherein one of a photoresist layer or a polyimide layer is used as the leveling auxiliary layer.

Claim 8

Method according to claim 1, wherein the structuring of the second layer is implemented using an essentially anisotropic etching process.

Claim 9

Method according to claim 7, wherein the anisotropic etching process has a polymerizing gas additive.

Claim 10

Method according to claim 1, wherein after the sacrificial layer is produced, a phototechnique layer is applied that covers at least the location of the capacitor plate electrode with resist to remove exposed parts of the sacrificial layer above the field oxide.

Claim 11

Method according to claim 1, wherein a fourth layer is deposited on the third layer before the leveling auziliary layer is applied.

Claim 12

Method according to claim 10, wherein one of silicon nitride or silicon oxynitride is used as the fourth layer.

Claim 13

Method according to claim 1, wherein at least the third layer is anisotropically and selectively etched relative to the second layer after the partial removal of the auxiliary layer that exposes at least parts of the third layer.

Claim 14

Method according to claim 1, wherein the sacrificial layer is produced by thermal oxidation of the second layer.

Claim 15

Method according to claim 13, wherein a lateral expanse of the sacrificial layer is set by the thermal oxidation.

Claim 16

Method according to claim 1, wherein the sacrificial layer is produced by selective deposition of one of polycrystalline silicon, a refractory metal or a metal silicide on the second layer.

Claim 17

Method according to claim 1, wherein the sacrificial layer is produced by selective epitaxy of polycrystalline silicon on the second layer.

Claim 18

Method according to claim 1, wherein the sacrificial layer is produced by surface-wide deposition of silicide-forming metals and by a subsequent silicidation process.

Claim 19

Method for manufacturing a trench capacitor of a one-transistor memory cell in a semiconductor substrate, comprising the steps of: forming a trench overlapping with a field oxide that isolates various cells and forming a first capacitor electrode of the trench capacitor, manufacturing a first layer on a surface of the semiconductor substrate and on a surface of the first capacitor electrode; applying a second layer on the first layer and on the field oxide, and applying third layer over the second layer and a fourth layer over the third layer and a leveling auxiliary layer over the fourth layer; removing the auxiliary layer at least until parts of the fourth layer are exposed, removing the exposed part of the fourth layer and removing parts of the third layer that are under the exposed parts of the fourth layer at least until parts of the surface of the second layer are exposed; completely removing the auxiliary layer to produce a sacrificial layer at least on the exposed part of the surface of the second layer; completely removing the third and fourth layers still situated on the surface of the second layer with the exception of the sacrificial layer, and structuring the second layer using the sacrificial layer as a mask to form a capacitor plate electrode of the trench capacitor.

Claim 20

Method for manufacturing a trench capacitor of a one-transistor memory cell in a semiconductor substrate, comprising the steps of: forming a trench overlapping with a field oxide that isolates various cells and forming a first capacitor electrode of the trench capacitor, manufacturing a first layer on a surface of the semiconductor substrate and on a surface of the first capacitor electrode; applying a second layer on the first layer and on the field oxide, and applying third layer over the second layer and a fourth layer over the third layer and a leveling auxiliary layer over the fourth layer; removing the auxiliary layer at least until parts of the fourth layer are exposed, removing the exposed part of the fourth layer and removing parts of the third layer that are under the exposed parts of the fourth layer at least until parts of the surface of the second layer are exposed; completely removing the auxiliary layer to produce a sacrificial layer at least on the exposed part of the surface of the second layer; completely removing the third and fourth layers still situated on the surface of the second layer with the exception of the sacrificial layer, and structuring the second layer using the sacrificial layer as a mask to form a capacitor plate electrode of the trench capacitor.

Claim 21

Method according to claim 18, wherein one of a thermal or deposited silicon oxide is used as the first layer.

Claim 22

Method according to claim 18, wherein one of a double layer or a triple layer composed of silicon oxide and silicon nitride as constituents is used as the first layer.

Claim 23

Method according to claim 18, wherein a doped polycrystalline silicon layer is used as the second layer.

Claim 24

Method according to claim 18, wherein one of a thermal or deposited silicon oxide is used as the third layer.

Claim 25

Method according to claim 18, wherein one of a photoresist layer or a polyimide layer is used as the leveling auxiliary layer.

Claim 26

Method according to claim 18, wherein the structuring of the second layer is implemented using an essentially anisotropic etching process.

Claim 27

Method according to claim 24, wherein the anisotropic etching process has a polymerizing gas additive.

Claim 28

Method according to claim 18, wherein after the sacrificial layer is produced, a phototechnique layer is applied that covers at least the location of the capacitor plate electrode with resist to remove exposed parts of the sacrificial layer above the field oxide.

Claim 29

Method according to claim 18, wherein one of silicon nitride or silicon oxynitride is used as the fourth layer.

Claim 30

Method according to claim 18, wherein the fourth and third layers are anisotropically and selectively etched relative to the second layer after the partial removal of the auxiliary layer that exposes at least parts of the underlying fourth layer.

Claim 31

Method according to claim 18, wherein the sacrificial layer is produced by thermal oxidation of the second layer.

Claim 32

Method according to claim 29, wherein a lateral expanse of the sacrificial layer is set by the thermal oxidation.

Claim 33

Method according to claim 18, wherein the sacrificial layer is produced by selective deposition of one of polycrystalline silicon, a refractory metal or a metal silicide on the second layer.

Claim 34

Method according to claim 18, wherein the sacrificial layer is produced by selective epitaxy of polycrystalline silicon on the second layer.

Claim 35

Method according to claim 18, wherein the sacrificial layer is produced by surface-wide deposition of silicide-forming metals and by a subsequent silicidation process.