Bus interface controller for computer graphics

Claim 2

A bus multiplexer having a plurality of multi-bit channels, a clock signal, a mux-control signal, an output enable signal, and an out-count signal, the bus multiplexer comprising: (a) a first multiplexer means for selecting any one of the multi-bit channels wherein the first multiplexer means has a plurality of multi-bit channel inputs wherein each multi-bit channel input is connected to a separate one of the multi-bit channels, a first select input connected to the mux-control signal and a first mux output channel, wherein the first multiplexer means selects a multi-bit channel in response to the mux-control signal; (b) a first data latching means for latching the first mux output channel having a first clock enable signal input connected to the clock signal, a first channel input connected to the first mux output channel, and wherein the first data latching means further comprises a first data output channel; (c) a second data latching means for latching the out-count signal having a second clock enable input connected to the clock signal, a second data input connected to the out-count signal, and wherein the second data latching means further comprises a first data output signal; (d) a third data latching means for latching the output enable signal having a third clock enable input connected to the clock signal, a third data input connected to the output enable signal, and wherein the third data latching means further comprises a second data output signal; (e) a first buffer means for transmitting a channel connected to the first mux output channel having a first buffer output channel; (f) a second multiplexer means for selecting a multiplexed multi-bit channel having a second select input connected to the first data output signal, a latched channel input connected to the first data output channel, and a buffered channel input connected to the first buffer output channel, wherein the second multiplexer further comprises a second mux output channel wherein the multiplexed multi-bit channel is selected in response to the first data output signal; and (g) a second buffer means for gating a signal having a transmit control connected to the second data output signal with a second buffer input connected to the second mux output channel, the second buffer means having a second buffer output connected to any one of the plurality of multi-bit channels.

Claim 3

The apparatus of claim 1 wherein: (a) the first multiplexer means is an 8 to 1 encoder; (b) the second multiplexer means is a 2 to 1 encoder; (c) the first data latching means and second data latching means further comprise D flip-flop circuits; (d) the apparatus is embedded in a semiconductor material comprising gallium arsenide; (e) the multi-bit channels include tri-state outputs; (f) the clock signal frequency is at least 25 megahertz; and (g) the multi-bit channels are TTL/CMOS compatible.

Claim 4

A bus interface controller for use in a digital information system having a plurality of multi-bit channels, a clock control signal, an output enable signal, an out-count signal and a mux-control signal wherein the bus interface controller comprises: (a) a plurality of bus multiplexers, each bus multiplexer comprising: (i) a first multiplexer means for selecting any one of the multi-bit channels wherein the first multiplexer means has a plurality of multi-bit channel inputs wherein each multi-bit channel input is connected to a separate one of the multi-bit channels, a first select input connected to the mux-control signal, and a first mux output channel, wherein the first multiplexer means selects a multi-bit channel in response to the mux-control signal; (ii) a first data latching means for latching the first mux output channel having a first clock enable signal input connected to the clock signal, a first channel input connected to the first mux output channel, and wherein the first data latching means further comprises a first data output channel; (iii) a second data latching means for latching the out-count signal having a second clock enable input connected to the clock signal, a second data input connected to the out-count signal, and wherein the second data latching means further comprises a first data output signal; (iv) a third data latching means for latching the output enable signal having a third clock enable input connected to the clock signal, a third data input connected to the output enable signal, and wherein the third data latching means further comprises a second data output signal; (v) a first buffer means for transmitting a channel connected to the first mux output channel having a first buffer output channel; (vi) a second multiplexer means for selecting a multiplexed multi-bit channel having a second select input connected to the first data output signal, a latched channel input connected to the first data output channel, and a buffered channel input connected to the first buffer output channel, wherein the second multiplexer further comprises a second mux output channel wherein the multiplexed multi-bit channel is selected in response to the first data output signal; and (vii) a second buffer means for gating a signal having a transmit control connected to the second data output signal with a second buffer input connected to the second mux output channel, the second buffer means having a second buffer output connected to any one of the plurality of multi-bit channels.

Claim 5

A bus interface controller for use in a digital information system having a plurality of multi-bit channels, a clock control signal, an output enable signal, an out-count signal and a mux-control signal wherein the bus interface controller comprises: (a) a plurality of bus multiplexers, each bus multiplexer comprising: (i) a first multiplexer means for selecting any one of the multi-bit channels wherein the first multiplexer means has a plurality of multi-bit channel inputs wherein each multi-bit channel input is connected to a separate one of the multi-bit channels, a first select input connected to the mux-control signal, and a first mux output channel, wherein the first multiplexer means selects a multi-bit channel in response to the mux-control signal; (ii) a first data latching means for latching the first mux output channel having a first clock enable signal input connected to the clock signal, a first channel input connected to the first mux output channel, and wherein the first data latching means further comprises a first data output channel; (iii) a second data latching means for latching the out-count signal having a second clock enable input connected to the clock signal, a second data input connected to the out-count signal, and wherein the second data latching means further comprises a first data output signal; (iv) a third data latching means for latching the output enable signal having a third clock enable input connected to the clock signal, a third data input connected to the output enable signal, and wherein the third data latching means further comprises a second data output signal; (v) a first buffer means for transmitting a channel connected to the first mux output channel having a first buffer output channel; (vi) a second multiplexer means for selecting a multiplexed multi-bit channel having a second select input connected to the first data output signal, a latched channel input connected to the first data output channel, and a buffered channel input connected to the first buffer output channel, wherein the second multiplexer further comprises a second mux output channel wherein the multiplexed multi-bit channel is selected in response to the first data output signal; and (vii) a second buffer means for gating a signal having a transmit control connected to the second data output signal with a second buffer input connected to the second mux output channel, the second buffer means having a second buffer output connected to any one of the plurality of multi-bit channels.

Claim 6

The apparatus of claim 3 wherein: (a) the first multiplexer means is an 8 to 1 encoder; (b) the second multiplexer means is a 2 to 1 encoder; (c) the first data latching means and second data latching means comprise D flip-flop circuits; (d) the apparatus is embedded in a semiconductor material comprising gallium arsenide; (e) the multi-bit channels include tri-state outputs; (f) the clock signal frequency is at least 25 megahertz; and (g) the multi-bit channels are TTL/CMOS compatible.