US5068704A
Expired / Lapsed
US
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Method of manufacturing semiconductor device
Assignee: Toshiba Corp
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Filing: 1990-05-08
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Granted: 1991-11-26
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Expires: 2010-05-08
Abstract
Abstract A method of manufacturing a semiconductor device comprising the steps of bringing a mirror-polished surface of a first semiconductor substrate of a first conductivity type into contact with a mirror-polished surface of a second semiconductor substrate of a second conductivity type having an impurity concentration which is lower than that of said first conductivity type, in a clean atmosphere, and thermally heating said first and second semiconductor substrates so that they unite. Impurity is diffused from said first semiconductor substrate into said second semiconductor substrate, thereby forming a diffusion layer of a first conductivity type in said second semiconductor substrate. A total amount of impurity of said diffusion layer is 1×10 13 /cm 2 to 2×10 15 /cm 2 , to form a pn junction in said second semiconductor substrate.
Inventors
- 👤 Akio Nakagawa
- 👤 Kaoru Imamura
- 👤 Ryo Sato
- 👤 Tadahide Hoshi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 13:43
CPC Classifications
H; H10; H10D; H10D12/00; H10D12/01; H10D12/031; H10D12/032; H10P; H10P10/00; H10P10/12; H10P10/128; H10P32/00; H10P32/10; H10P32/15; Y; Y10; Y10S; Y10S148/00; Y10S148/012; Y10S148/157
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
111 words
In a semiconductor device, the improvement comprising a first semiconductor substrate of a first conductivity type and a second semiconductor substrate of a second conductivity type, which is bonded to said first semiconductor substrate, wherein an emitter region of the first conductivity type is formed in the bonding surface of said second substrate and a total amount per unit area of impurity of said emitter region is 1 × 10 13 /cm 2 to 2 × 10 15 /cm 2 , the thickness of said emitter region is 7 μm or less, and a number of crystal defects exist on the bonding interface, so that an emitter injection efficiency is lowered.
Claim 2
Dependent Claim
111 words
In a semiconductor device, the improvement comprising a first semiconductor substrate of a first conductivity type and a second semiconductor substrate of a second conductivity type, which is bonded to said first semiconductor substrate, wherein an emitter region of the first conductivity type is formed in the bonding surface of said second substrate and a total amount per unit area of impurity of said emitter region is 1 × 10 13 /cm 2 to 2 × 10 15 /cm 2 , the thickness of said emitter region is 7 μm or less, and a number of crystal defects exist on the bonding interface, so that an emitter injection efficiency is lowered.
Claim 3
Dependent Claim
20 words
A semiconductor device according to claim 1, in which said first and second semiconductor substrates are doped with lifetime killer.
Claim 4
Dependent Claim
20 words
A semiconductor device according to claim 1, in which the thickness of said emitter region is 3 to 6 μm.
Claim 5
Dependent Claim
32 words
A semiconductor device according to claim 1, in which the resistivity of said first semiconductor substrate is 0.01 to 0.05 Ω·cm, and the thickness of said emitter is 3 to 7 μm.
Claim 6
Dependent Claim
21 words
A semiconductor device according to claim 1, in which said first and second semiconductor substrates have different indices of a plane.
Claim 7
Dependent Claim
35 words
A semiconductor device according to claim 1, in which a total amount per unit area of impurity of said emitter is 1 × 10 14 /cm 2 to 1 × 10 15 /cm 2 .
Claim 8
Dependent Claim
148 words
A conductivity modulation type MOS filed effect transistor, comprising a semiconductor substrate of a first conductivity type and a second semiconductor substrate of a second conductivity type, which is bonded to said first semiconductor substrate, wherein an emitter region of the first conductivity type is formed in the bonding surface of said second substrate and a total amount per unit area of impurity of said emitter region is 1 × 10 13 /cn 2 to 2 × 10 15 /cm 2 , the thickness of said emitter region is 7 μm or less, a number of crystal defects exist on the bonding interface, so that an emitter injection efficiency is lowered, source and drain regions are formed in the surface of the second substrate, a gate insulating layer is formed on the surface of the second substrate, and a gate electrode is formed on the gate insulating layer.
Claim 9
Dependent Claim
148 words
A conductivity modulation type MOS filed effect transistor, comprising a semiconductor substrate of a first conductivity type and a second semiconductor substrate of a second conductivity type, which is bonded to said first semiconductor substrate, wherein an emitter region of the first conductivity type is formed in the bonding surface of said second substrate and a total amount per unit area of impurity of said emitter region is 1 × 10 13 /cn 2 to 2 × 10 15 /cm 2 , the thickness of said emitter region is 7 μm or less, a number of crystal defects exist on the bonding interface, so that an emitter injection efficiency is lowered, source and drain regions are formed in the surface of the second substrate, a gate insulating layer is formed on the surface of the second substrate, and a gate electrode is formed on the gate insulating layer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-11-25 | 1995-05-27 | 1995-11-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-11-25 | 1999-05-27 | 1999-11-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-11-25 | 2003-05-27 | 2003-11-26 | $7700.00 | Window Closed / Lapsed |