US5068207A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for producing a planar surface in integrated circuit manufacturing
Assignee: Nokia Bell Labs
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Filing: 1990-04-30
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Granted: 1991-11-26
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Expires: 2010-04-30
Abstract
Abstract A planar surface is produced in integrated circuit processing by patterning a bilevel structure of a conductor and a sacrificial layer followed by directional deposition of a dielectric and lift off of the sacrificial layer. An additional dielectric layer may now be deposited if desired.
Inventors
- 👤 Ajit S. Manocha
- 👤 Chen-Hua D. Yu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 22:28
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/031; H10W20/056; H10W20/058; Y; Y10; Y10S; Y10S148/00; Y10S148/10; Y10S438/00; Y10S438/942; Y10S438/948; Y10S438/951
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
96 words
A method of integrated circuit manufacturing comprising the steps of patterning a bilevel structure on a substrate to expose selected portions of said substrate, said bilevel structure comprising a conductor layer adjacent to said substrate and a sacrificial layer on said conductor layer, said sacrificial layer material comprises a glass; depositing a first dielectric in a direction substantially perpendicular to the substrate surface, said first dielectric covering no more than a portion of the sidewalls of said sacrificial layer; and, lifting off said sacrificial layer by wet etching to leave said first dielectric on said substrate.
Claim 2
Independent Claim
96 words
A method of integrated circuit manufacturing comprising the steps of patterning a bilevel structure on a substrate to expose selected portions of said substrate, said bilevel structure comprising a conductor layer adjacent to said substrate and a sacrificial layer on said conductor layer, said sacrificial layer material comprises a glass; depositing a first dielectric in a direction substantially perpendicular to the substrate surface, said first dielectric covering no more than a portion of the sidewalls of said sacrificial layer; and, lifting off said sacrificial layer by wet etching to leave said first dielectric on said substrate.
Claim 3
Dependent Claim
16 words
A method as recited in claim 1 in which said glass comprises a spin on glass.
Claim 4
Dependent Claim
21 words
A method as recited in claim 1 comprising the further step of depositing a second dielectric after said lifting off step.
Claim 5
Dependent Claim
14 words
A method as recited in claim 1 in which said conductor comprises a metal.
Claim 6
Dependent Claim
14 words
A method as recited in claim 1 in which said conductor comprises a silicide.
Claim 7
Dependent Claim
15 words
A method as recited in claim 1 in which said conductor comprises a doped silicon.
References Cited (Backward Citations)
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Cited
US4328263A
Cited
JPS5877247A
Cited
US4432134A
Cited
JPS602835A
Cited
JPS61288445A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-11-25 | 1995-05-27 | 1995-11-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-11-25 | 1999-05-27 | 1999-11-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-11-25 | 2003-05-27 | 2003-11-26 | $7700.00 | Window Closed / Lapsed |