Patent US5068199A successfully refreshed from Google Patents.
US5068199A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for anodizing a polysilicon layer lower capacitor plate of a DRAM to increase capacitance
Assignee: Micron Technology Inc
•
Filing: 1991-05-06
•
Granted: 1991-11-26
•
Expires: 2011-05-06
Abstract
Abstract A method for fabricating a DRAM cell having enhanced-capacitance attributable to the use of a porous structured polycrystalline silicon layer storage node capacitor plate. The present invention is particularly applicable to DRAM cells which employ a stacked capacitor design. Such designs generally employ a conductively-doped polycrystalline silicon layer as the storage node, or lower, capacitor plate. A microstructure is formed by anodizing the storage node plate layer in a solution of hydrofluoric acid to produce microstructures resembling elongated pores in the storage node plate layer. This is followed by the deposition of a thin conformal (typically less than 100 Angstroms) silicon nitride layer which in turn is followed by the deposition of a second polycrystalline silicon (poly) layer, which functions as the capacitor field plate. Since the nitride layer is thin in comparison to the elongated pores in the storage node plate layer, capacitive area is substantially augmented. Cell capacitance can be increased by more than 1,000 percent using a storage node plate having microstructures thus formed.
Inventors
- 👤 Gurtej S. Sandhu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 02:26
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10D; H10D1/00; H10D1/01; H10D1/045; H10D1/047; H10D1/60; H10D1/68; H10D1/692; H10D1/711; H10D1/712; H10P; H10P50/00; H10P95/00; Y; Y10; Y10S; Y10S438/00; Y10S438/96
Claims Analysis
Total Claims: 46
Claim 1
Independent Claim
231 words
A method of fabricating a storage capacitor having an intrinsic silicon layer doped with an impurity to produce an extrinsic first doped silicon conductive layer forming a storage node capacitor plate comprising the following steps: a) anodizing said first doped silicon layer, said anodizing producing a porous upper surface by consuming portions of said first doped silicon layer to produce micro structures resembling elongated pores, a porosity of said porous upper surface measured by a porous film density, said porous film density equal to the percent of weight loss for a given volume of said first doped silicon layer experience during said anodizing, said anodizing increasing a surface area of said storage node capacitor plate; b) depositing a dielectric layer to overlie said first doped silicon layer, said dielectric layer having lower and upper surfaces, the porous upper surface of said first doped silicon layer being in contact at all points with the lower surface of said dielectric layer, said dielectric layer being substantially conformal with the porous upper surface of said first doped silicon layer; and c) depositing of an intrinsic silicon layer doped with an impurity to produce an extrinsic second doped silicon conductive layer to overlie said dielectric layer, said second doped silicon layer having lower and upper surfaces, said lower surface being in contact with the upper surface of said dielectric layer and being substantially conformal thereto.
Claim 2
Independent Claim
231 words
A method of fabricating a storage capacitor having an intrinsic silicon layer doped with an impurity to produce an extrinsic first doped silicon conductive layer forming a storage node capacitor plate comprising the following steps: a) anodizing said first doped silicon layer, said anodizing producing a porous upper surface by consuming portions of said first doped silicon layer to produce micro structures resembling elongated pores, a porosity of said porous upper surface measured by a porous film density, said porous film density equal to the percent of weight loss for a given volume of said first doped silicon layer experience during said anodizing, said anodizing increasing a surface area of said storage node capacitor plate; b) depositing a dielectric layer to overlie said first doped silicon layer, said dielectric layer having lower and upper surfaces, the porous upper surface of said first doped silicon layer being in contact at all points with the lower surface of said dielectric layer, said dielectric layer being substantially conformal with the porous upper surface of said first doped silicon layer; and c) depositing of an intrinsic silicon layer doped with an impurity to produce an extrinsic second doped silicon conductive layer to overlie said dielectric layer, said second doped silicon layer having lower and upper surfaces, said lower surface being in contact with the upper surface of said dielectric layer and being substantially conformal thereto.
Claim 3
Dependent Claim
16 words
The method of claim 1, wherein said first and second doped silicon layers comprise polycrystalline silicon.
Claim 4
Dependent Claim
16 words
The method of claim 1, wherein said first and second doped silicon layers comprise monocrystalline silicon.
Claim 5
Dependent Claim
16 words
The method of claim 1, wherein said first and second doped silicon layers are positively doped.
Claim 6
Dependent Claim
25 words
The method of claim 4, wherein said impurity is a trivalent atom comprising aluminum, boron and gallium, said trivalent atom effecting said positively doped layers.
Claim 7
Dependent Claim
17 words
The method of claim 1, wherein said first and second doped silicon layers are negatively doped layers.
Claim 8
Dependent Claim
25 words
The method of claim 6, wherein said impurity is a pentavalent atom comprising arsenic, antimony, and phosphorus, said pentavalent atom effecting said negatively doped layers.
Claim 9
Dependent Claim
33 words
The method of claim 1, wherein said first and second doped silicon layers are oppositely doped, one of said doped layers being negatively doped and one of said doped layers being positively doped.
Claim 10
Dependent Claim
25 words
The method of claim 8, wherein said impurity is a trivalent atom comprising aluminum, boron and gallium, said trivalent atom effecting said positively doped layers.
Claim 11
Dependent Claim
25 words
The method of claim 8, wherein said impurity is a pentavalent atom comprising arsenic, antimony, and phosphorus, said pentavalent atom effecting said negatively doped layers.
Claim 12
Dependent Claim
19 words
The method of claim 1, wherein said depositing of the dielectric layer further comprises depositing a silicon nitride layer.
Claim 13
Dependent Claim
18 words
The method of claim 11 wherein the thickness of said silicon nitride layer is less than 100 Angstroms.
Claim 14
Dependent Claim
55 words
The method of claim 1, wherein said anodizing further comprises submerging said first doped silicon layer in a container of electrolytic solution comprising hydrofluoric acid and subjecting said first doped silicon layer and said electrolytic solution to an electrolytic current, said current generated between two electrodes, one being an anode and one being a cathode.
Claim 15
Dependent Claim
15 words
The method of claim 13, wherein said anode further comprises said first doped silicon layer.
Claim 16
Dependent Claim
23 words
The method of claim 13, wherein said first doped silicon layer is a portion of a semiconductor wafer, said anode comprising said wafer.
Claim 17
Dependent Claim
17 words
The method of claim 13, wherein said container is defined by walls, said cathode comprising said walls.
Claim 18
Dependent Claim
25 words
The method of claim 13, wherein said cathode further comprises a platinum electrode immersed in said electrolytic solution parallel to said first doped silicon layer.
Claim 19
Dependent Claim
37 words
The method of claim 13, further comprising applying said electrolytic current within the range of 10 mA/cm 2 and 100 mA/cm 2 in said hydrofluoric acid solution having a concentration between 10 to 60 percent by weight.
Claim 20
Dependent Claim
30 words
The method of claim 18, further comprising regulating said porous film density within the range of 20 to 70 percent, with a preferred porous film density of about 45 percent.
Claim 21
Dependent Claim
47 words
The method of claim 13, further comprising the step of a first texturizing of the upper surface of said first doped silicon layer prior to said anodizing to produce three-dimensional asperities to increase current flow and initiate pores in said first doped silicon layer during said anodizing.
Claim 22
Dependent Claim
60 words
The method of claim 20, wherein said first texturizing comprises: a) growing a layer of oxide on said first doped silicon layer prior to said anodizing to produce inhomogeneities to increase current flow and initiate pores in said first doped silicon layer during said anodizing; and b) removing of said layer of oxide to expose said first doped silicon layer.
Claim 23
Dependent Claim
19 words
The method of claim 21, wherein said growing of said layer of oxide is accomplished with a wet oxidation.
Claim 24
Dependent Claim
15 words
The method of claim 21, wherein said removing is accomplished with a wet oxide etch.
Claim 25
Dependent Claim
33 words
The method of claim 13, further comprising the step of a second texturizing of the porous upper surface subsequent to said anodizing to increase the surface area of said storage node capacitor plate.
Claim 26
Dependent Claim
44 words
The method of claim 24, wherein said second texturizing comprises: a) growing a layer of oxide on the porous upper surface subsequent to said anodizing to increase porous film density; and b) removing of said layer of oxide to expose said porous upper surface.
Claim 27
Dependent Claim
19 words
The method of claim 23, wherein said growing of said layer of oxide is accomplished with a wet oxidation.
Claim 28
Dependent Claim
15 words
The method of claim 23, wherein said removing is accomplished with a wet oxide etch.
Claim 29
Independent Claim
292 words
A method of fabricating an enhanced-capacitance DRAM cell comprising the following steps: a) constructing a field-effect transistor (FET) on a silicon substrate, a first portion of said substrate being conductively-doped to function as the FET's access node junction and a second portion of said substrate being conductively-doped to function as the FET's storage node junction; b) fabricating a storage capacitor having an intrinsic silicon layer doped with an impurity to produce an extrinsic first doped silicon conductive layer forming a storage node capacitor plate in electrical communication with said storage node junction comprising the following steps: 1) anodizing said first doped silicon layer, said anodizing producing a porous upper surface by consuming portions of said first doped silicon layer to produce micro structures resembling elongated pores, a porosity of said porous upper surface measured by a porous film density, said porous film density equal to the percent of weight loss for a given volume of said first doped silicon layer experience during said anodizing, said anodizing increasing a surface area of said storage node capacitor plate; 2) depositing a dielectric layer to overlie said first doped silicon layer, said dielectric layer having lower and upper surfaces the porous upper surface of said first doped silicon layer being in contact at all points with the lower surface of said dielectric layer, said dielectric layer being substantially conformal with the porous upper surface of said first doped silicon layer; and 3) depositing of an intrinsic silicon layer doped with an impurity to produce an extrinsic second doped silicon conductive layer to overlie said dielectric layer, said second doped silicon layer having lower and upper surfaces, said lower surface being in contact with the upper surface of said dielectric layer and being substantially conformal thereto.
Claim 30
Independent Claim
292 words
A method of fabricating an enhanced-capacitance DRAM cell comprising the following steps: a) constructing a field-effect transistor (FET) on a silicon substrate, a first portion of said substrate being conductively-doped to function as the FET's access node junction and a second portion of said substrate being conductively-doped to function as the FET's storage node junction; b) fabricating a storage capacitor having an intrinsic silicon layer doped with an impurity to produce an extrinsic first doped silicon conductive layer forming a storage node capacitor plate in electrical communication with said storage node junction comprising the following steps: 1) anodizing said first doped silicon layer, said anodizing producing a porous upper surface by consuming portions of said first doped silicon layer to produce micro structures resembling elongated pores, a porosity of said porous upper surface measured by a porous film density, said porous film density equal to the percent of weight loss for a given volume of said first doped silicon layer experience during said anodizing, said anodizing increasing a surface area of said storage node capacitor plate; 2) depositing a dielectric layer to overlie said first doped silicon layer, said dielectric layer having lower and upper surfaces the porous upper surface of said first doped silicon layer being in contact at all points with the lower surface of said dielectric layer, said dielectric layer being substantially conformal with the porous upper surface of said first doped silicon layer; and 3) depositing of an intrinsic silicon layer doped with an impurity to produce an extrinsic second doped silicon conductive layer to overlie said dielectric layer, said second doped silicon layer having lower and upper surfaces, said lower surface being in contact with the upper surface of said dielectric layer and being substantially conformal thereto.
Claim 31
Dependent Claim
38 words
The method of claim 28, further comprises: a) forming an oxide layer to provide a texturized surface; b) performing a wet oxidation to form said oxide layer; and c) removing said oxide layer with a wet oxide etch.
Claim 32
Dependent Claim
19 words
The method of claim 28, wherein said first and second doped silicon layers comprise polycrystalline silicon and monocrystalline silicon.
Claim 33
Dependent Claim
55 words
The method of claim 28, further comprising said first and second doped silicone layers being positively doped, said first and second doped silicon layers being negatively doped, and said first and second doped silicon layers being oppositely doped, one of said doped layers being negatively doped and one of said doped layers being positively doped.
Claim 34
Dependent Claim
17 words
The method of claim 28, wherein said impurity is a trivalent atom comprising aluminum, boron and gallium.
Claim 35
Dependent Claim
17 words
The method of claim 28, wherein said impurity is a pentavalent atom comprising arsenic, antimony, and phosphorus.
Claim 36
Dependent Claim
19 words
The method of claim 28, wherein said depositing of the dielectric layer further comprises depositing a silicon nitride layer.
Claim 37
Dependent Claim
18 words
The method of claim 34, wherein the thickness of said silicon nitride layer is less than 100 Angstroms.
Claim 38
Dependent Claim
55 words
The method of claim 28, wherein said anodizing further comprises submerging said first doped silicon layer in a container of electrolytic solution comprising hydrofluoric acid and subjecting said first doped silicon layer and said electrolytic solution to an electrolytic current, said current generated between two electrodes, one being an anode and one being a cathode.
Claim 39
Dependent Claim
18 words
The method of claim 36, wherein said anode comprises said first doped silicon layer and said silicon substrate.
Claim 40
Dependent Claim
33 words
The method of claim 36, wherein said container is defined by walls, said cathode comprising said walls and a platinum electrode immersed in said electrolytic solution parallel to said first doped silicon layer.
Claim 41
Dependent Claim
37 words
The method of claim 36, further comprising applying said electrolytic current within the range of 10 mA/cm 2 and 100 mA/cm 2 in said hydrofluoric acid solution having a concentration between 10 to 60 percent by weight.
Claim 42
Dependent Claim
30 words
The method of claim 39, further comprising regulating said porous film density within the range of 20 to 70 percent, with a preferred porous film density of about 45 percent.
Claim 43
Dependent Claim
45 words
The method of claim 36, further comprising the step of texturizing of the upper surface of said first doped silicon layer prior to said anodizing to produce three-dimensional asperities to increase current flow and initiate pores in said first doped silicon layer during said anodizing.
Claim 44
Dependent Claim
59 words
The method of claim 41, wherein said texturizing comprises: a) growing a layer of oxide on said first doped silicon layer prior to said anodizing to produce inhomogeneities to increase current flow and initiate pores in said first doped silicon layer during said anodizing; and b) removing of said layer of oxide to expose said first doped silicon layer.
Claim 45
Dependent Claim
31 words
The method of claim 36, further comprising the step of texturizing of the porous upper surface subsequent to said anodizing to increase the surface area of said storage node capacitor plate.
Claim 46
Dependent Claim
43 words
The method of claim 43, wherein said texturizing comprises: a) growing a layer of oxide on the porous upper surface subsequent to said anodizing to increase porous film density; and b) removing of said layer of oxide to expose said porous upper surface.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-11-25 | 1995-05-27 | 1995-11-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-11-25 | 1999-05-27 | 1999-11-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-11-25 | 2003-05-27 | 2003-11-26 | $7700.00 | Window Closed / Lapsed |