Method of direct memory access control

Claim 1

For use in a system comprising an input/output device, a memory, a processor for controlling said input/output device and said memory, a processor bus connected to said memory and said processor and means connected between said input/output device and said processor bus for temporarily storing direct memory access information which is to be stored in said memory, a method of controlling direct memory access from said input/output device to said memory via said processor bus, comprising the steps of: receiving and storing direct memory access information from said input/output device into said temporary storing means via a signal line having a significant delay; thereafter requesting from said processor a right to usage of said processor bus for transmission of direct memory access information after said direct memory access information is stored in said temporary storing means; and transmitting all of the direct memory access information stored in said temporary storing means to said processor bus for storage in said memory.

Claim 6

A method of direct memory access control comprising the steps of: storing an input/output command from a processor to an input/output device in a first buffer register; storing direct memory access information to be transmitted from said input/output device to a memory temporarily in a second buffer register; transmitting a direct memory access request from control means for said buffer registers to said processor after all direct memory access information is stored in said second buffer register; granting the direct memory access by sending a permission signal from said processor to said control means; sending the input/output command stored in said first buffer register to said input/output device; and thereafter requesting from said processor a right to usage of said processor bus for transmission of direct memory access information; and transmitting said direct memory access information from said second buffer register to said memory after completion of the sending of said input/output command to said input/output device.

Claim 7

A method of direct memory access control comprising the steps of: storing an input/output command from a processor to an input/output device in a first buffer register; storing direct memory access information to be transmitted from said input/output device to a memory temporarily in a second buffer register; transmitting a direct memory access request from control means for said buffer registers to said processor after all direct memory access information is stored in said second buffer register; granting the direct memory access by sending a permission signal from said processor to said control means; sending the input/output command stored in said first buffer register to said input/output device; and thereafter requesting from said processor a right to usage of said processor bus for transmission of direct memory access information; and transmitting said direct memory access information from said second buffer register to said memory after completion of the sending of said input/output command to said input/output device.

Claim 12

A method of direct memory access for a system which comprises an input/output device, a memory, a processor, and a processor bus connecting said system components, and which operates in such a way that said input/output device issues a direct memory access request to said processor, and, when said processor grants the request, direct access to said memory through said processor bus is effected, said method comprising the steps of: obtaining a usage right for said processor bus and transmitting and storing temporarily an input/output device controlling command from said processor to said input/output device in a first buffer register; transmitting and temporarily storing direct memory access information from said input/output device to said memory in a second buffer register; transmitting the input/output device controlling command from said first buffer register to said input/output device; terminating the execution of the input/output device controlling command and sending a usage right for said processor bus to a means for controlling said first and second buffer registers; and effecting direct memory access execution by transmitting the direct memory access information from said second buffer register to said memory.

Claim 13

A method of direct memory access for a system which comprises an input/output device, a memory, a processor, and a processor bus connecting said system components, and which operates in such a way that said input/output device issues a direct memory access request to said processor, and, when said processor grants the request, direct access to said memory through said processor bus is effected, said method comprising the steps of: obtaining a usage right for said processor bus and transmitting and storing temporarily an input/output device controlling command from said processor to said input/output device in a first buffer register; transmitting and temporarily storing direct memory access information from said input/output device to said memory in a second buffer register; transmitting the input/output device controlling command from said first buffer register to said input/output device; terminating the execution of the input/output device controlling command and sending a usage right for said processor bus to a means for controlling said first and second buffer registers; and effecting direct memory access execution by transmitting the direct memory access information from said second buffer register to said memory.

Claim 14

A method of direct memory access control comprising the steps of: storing an input/output device controlling command being sent from a processor to an input/output device in a first buffer register; storing direct memory access information being sent from said input/output device to said memory in a second buffer registers; transmitting a direct memory access request from control means for said first and second buffer registers to said processor; granting the direct memory access by giving the usage right for the processor bus to said means for controlling said first and second buffer registers; transmitting the input/output device controlling command from said first buffer register to said input/output device; executing the input/output device controlling command from said processor to said input/output device; and transmitting said direct memory access information from said second buffer register to said memory after termination of the execution of said input/output device controlling command.

Claim 15

A method of direct memory access control comprising the steps of: storing an input/output device controlling command being sent from a processor to an input/output device in a first buffer register; storing direct memory access information being sent from said input/output device to said memory in a second buffer registers; transmitting a direct memory access request from control means for said first and second buffer registers to said processor; granting the direct memory access by giving the usage right for the processor bus to said means for controlling said first and second buffer registers; transmitting the input/output device controlling command from said first buffer register to said input/output device; executing the input/output device controlling command from said processor to said input/output device; and transmitting said direct memory access information from said second buffer register to said memory after termination of the execution of said input/output device controlling command.