Analog to digital converters with convergence accelerating signals

Claim 2

Analog to digital converter comprising a charge storage or charge summation circuit which continuously up-integrates the input signal i e , followed by a comparator, a logic circuit which at periodically recurring instants defined by an oscillator, a timebase counter and a bistable stage, the time between two successive such instants being called a sub-measurement, connects via an analog switch a first reference current/voltage to the charge storage or charge summation circuit for additional integration and disconnects the previously up-integrated second reference current/voltage with the aid of a second analog switch and after a predefined number of oscillator pulse flanks after the next following passage of the output voltage of the charge storage or charge summation circuit through the comparator threshold switches off again the first reference current/voltage and the second reference current/voltage on again, a gate and a result counter contained in the logic circuit which by counting the oscillator pulses during the time in which the first or the second reference current/voltage is being up-integrated in addition to the input signal, determines a first digital value which is passed on to a measured value processing circuit, wherein at the input of the charge storage or charge summation circuit used for the input signal or at one of its other inputs, convergence accelerating signals are superimposed after every nth (n=1,2,3, . . . ) sub-measurement whereby the Taylor series expansions of these convergence accelerating signals according to time in the time interval of a sub-measurement are first or higher order polynomials.

Claim 3

Analog to digital converter according to claim 1, wherein the two reference currents/voltages have opposite polarity, at the periodically recurring instants in each case the reference current/voltage of polarity opposite to the polarity of the input signal is connected by the logic circuit via the corresponding analog switch, but the other is not connected.

Claim 4

Analog to digital converter according to claim 2, wherein the convergence accelerating signals are a function of the time t and/or of the input signal.

Claim 5

Analog to digital converter according to claim 3, wherein the convergence accelerating signals also contain components from derivatives and integrals of the input signal of any order.

Claim 6

Analog to digital converter according to claim 1, wherein the digital conversion result is corrected digitally by the magnitude of the convergence accelerating signals.

Claim 7

Analog to digital converter according to claim 1, wherein the mean value of the convergence accelerating signals is zero.

Claim 8

Analog to digital converter according to claim 6, wherein the convergence accelerating signals are injected capacitively.

Claim 9

Analog to digital converter according to claim 6, wherein the convergence accelerating signals during the down integration with the reference current/voltage connected at the start of the sub-measurement consist of terms proportional to the input signal, terms proportional to the references and terms proportional to the time elapsed since the beginning of the sub-measurement.

Claim 10

Analog to digital converter according to claim 8, wherein the resulting proportionality factor for the time elapse since the beginning of the sub-measurement is negative.

Claim 11

Analog to digital converter according to claim 8, wherein the resulting proportionality factors for the input signal and for the 2nd reference are positive and the resulting proportionality factor for the time elapse since the beginning of the sub-measurement is negative.

Claim 12

Analog to digital converter according to claim 8, wherein the aforementioned convergence accelerating signals are multiplied additionally by factors proportional to the nth power of the time elapse since the beginning of the sub-measurement, n=1,2,3, . . .

Claim 13

Analog to digital converter according to claim 8, wherein the resulting proportionality factor for the input signal is negative and the resulting proportionality factor for the time elapse since the beginning of the sub-measurement is zero.

Claim 14

Analog to digital converter comprising a charge storage or charge summation circuit which continuously up-integrates the input signal i e , followed by a comparator, a logic circuit which at periodically recurring instants determined by an oscillator, a timebase counter and a bistable stage, the time between two successive such instants being called a sub-measurement, connects via an analog switch a first reference current/voltage to the charge storage or charge summation circuit for additional integration and switches off the previously up-integrated second reference current/voltage with the aid of a second analog switch and, after a predefined number of oscillator pulse flanks after the next following passage of the output voltage of the charge storage or charge summation circuit through the comparator threshold value disconnects the first reference current/voltage again and connects the second reference current/voltage again, a gate and a result counter contained in the logic circuit which by counting the oscillator pulses in the time during which the first or the second reference current/voltage is being up-integrated in addition to the input signal, determines a first digital value which is passed on to a measured value processing circuit, wherein for every nth (n=1,2,3, . . . ) sub-measurement convergence accelerating signals, whereby the Taylors series expansions of these convergence accelerating signals according to time in the time interval of a sub-measurement are first or higher order polynomials, are completely or only in part as so-called partial terms in integral form, if the charge storage or charge summation circuit is an integrator, otherwise as transformation corresponding to the transformation constituted by the charge storage or charge summation circuit, connected via a summation circuit to the same comparator input as the output voltage of the charge storage or charge summation circuit or to a similarly acting comparator input or in inverted form to an inverting or opposite phase comparator input, and that the residual terms of the aforementioned convergence accelerating signals are superimposed on the input of the charge storage or charge summation circuit used for the input signal or on one of its other inputs, all this on condition that the signs of the second derivative of the sum of these integrated or transformed partial terms and the first derivative of the integrated or transformed input signal a) are opposite when using the same comparator input for the integrated or transformed partial terms as for the output voltage of the charge storage or charge summation circuit or b) are the same when using opposite phase comparator inputs for the signals specified under a).

Claim 15

Analog to digital converter comprising a charge storage or charge summation circuit which continuously up-integrates the input signal i e , followed by a comparator, a logic circuit which at periodically recurring instants determined by an oscillator, a timebase counter and a bistable stage, the time between two successive such instants being called a sub-measurement, connects via an analog switch a first reference current/voltage to the charge storage or charge summation circuit for additional integration and switches off the previously up-integrated second reference current/voltage with the aid of a second analog switch and, after a predefined number of oscillator pulse flanks after the next following passage of the output voltage of the charge storage or charge summation circuit through the comparator threshold value disconnects the first reference current/voltage again and connects the second reference current/voltage again, a gate and a result counter contained in the logic circuit which by counting the oscillator pulses in the time during which the first or the second reference current/voltage is being up-integrated in addition to the input signal, determines a first digital value which is passed on to a measured value processing circuit, wherein for every nth (n=1,2,3, . . . ) sub-measurement convergence accelerating signals, whereby the Taylors series expansions of these convergence accelerating signals according to time in the time interval of a sub-measurement are first or higher order polynomials, are completely or only in part as so-called partial terms in integral form, if the charge storage or charge summation circuit is an integrator, otherwise as transformation corresponding to the transformation constituted by the charge storage or charge summation circuit, connected via a summation circuit to the same comparator input as the output voltage of the charge storage or charge summation circuit or to a similarly acting comparator input or in inverted form to an inverting or opposite phase comparator input, and that the residual terms of the aforementioned convergence accelerating signals are superimposed on the input of the charge storage or charge summation circuit used for the input signal or on one of its other inputs, all this on condition that the signs of the second derivative of the sum of these integrated or transformed partial terms and the first derivative of the integrated or transformed input signal a) are opposite when using the same comparator input for the integrated or transformed partial terms as for the output voltage of the charge storage or charge summation circuit or b) are the same when using opposite phase comparator inputs for the signals specified under a).

Claim 16

Analog to digital converter comprising a charge storage or charge summation circuit which continuously up-integrates the input signal i e , followed by a comparator, a logic circuit which at periodically recurring instants defined by an oscillator, a timebase counter and a bistable stage, the time between two successive such instants being called a sub-measurement, connects via an analog switch a first reference current/voltage to the charge storage or charge summation circuit for additional integration and disconnects the previously up-integrating second reference current/voltage with the aid of a second analog switch, and after a predefined number of oscillator pulse flanks after the next following passage of the output voltage of the charge storage or charge summation circuit through the comparator threshold value, disconnects the first reference current/voltage again and connects the second reference current/voltage again, a gate and a result counter contained in the logic circuit which, by counting the oscillator pulses in the time during which the first or the second reference current/voltage is being up-integrated in addition to the input signal, determines a first digital value which is passed on to a measured value processing circuit, wherein for every nth (n=1,2,3, . . . ) sub-measurement convergence accelerating signals, whereby the Taylors series expansions of these convergence accelerating signals according to time in the time interval of a sub-measurement are first or higher order polynomials, are completely or only in part as so-called partial terms in integral form, when the charge storage or charge summation circuit is an integrator, otherwise as transformation corresponding to the transformation represented by the charge storage or charge summation circuit, connected via a summation circuit together with an integration or transformation constant not equal to zero, to the same comparator input as the output voltage of the charge storage or charge summation circuit or to a similarly acting comparator input, or in inverted form to an also inverting comparator input, and that the resitual terms of the aforementioned convergence accelerating signals are superimposed on the input of the charge storage or charge summation circuit used for the input signal or on one of its other inputs.

Claim 17

Analog to digital converter comprising a charge storage or charge summation circuit which continuously up-integrates the input signal i e , followed by a comparator, a logic circuit which at periodically recurring instants defined by an oscillator, a timebase counter and a bistable stage, the time between two successive such instants being called a sub-measurement, connects via an analog switch a first reference current/voltage to the charge storage or charge summation circuit for additional integration and disconnects the previously up-integrating second reference current/voltage with the aid of a second analog switch, and after a predefined number of oscillator pulse flanks after the next following passage of the output voltage of the charge storage or charge summation circuit through the comparator threshold value, disconnects the first reference current/voltage again and connects the second reference current/voltage again, a gate and a result counter contained in the logic circuit which, by counting the oscillator pulses in the time during which the first or the second reference current/voltage is being up-integrated in addition to the input signal, determines a first digital value which is passed on to a measured value processing circuit, wherein for every nth (n=1,2,3, . . . ) sub-measurement convergence accelerating signals, whereby the Taylors series expansions of these convergence accelerating signals according to time in the time interval of a sub-measurement are first or higher order polynomials, are completely or only in part as so-called partial terms in integral form, when the charge storage or charge summation circuit is an integrator, otherwise as transformation corresponding to the transformation represented by the charge storage or charge summation circuit, connected via a summation circuit together with an integration or transformation constant not equal to zero, to the same comparator input as the output voltage of the charge storage or charge summation circuit or to a similarly acting comparator input, or in inverted form to an also inverting comparator input, and that the resitual terms of the aforementioned convergence accelerating signals are superimposed on the input of the charge storage or charge summation circuit used for the input signal or on one of its other inputs.

Claim 18

Analog to digital converter according to claim 14, wherein the integration constant is chosen proportional to the square of the sum of the 2nd reference current/voltage and the input signal i e divided by 1+k (k=2nd reference current/voltage divided by the inverted 1st reference current/voltage), the magnitudes of both in each case being taken as ratio with respect to the 1st reference current/voltage, this for the case that the charge storage or charge summation circuit consists of a single integrating stage, otherwise the same additional conditioning holds for the integration constant as for the input signal in the charge storage or charge summation circuit.

Claim 19

Analog to digital converter according to claim 15, wherein the integration constant is produced by analog addition and multiplication circuits.

Claim 20

Analog to digital converter according to claim 15, wherein the integration constant is obtained by additional up-integration of the sum of the 2nd reference current/voltage and the input signal for the duration of the down-integration for the previous sub-measurement.

Claim 21

Analog to digital converter according to claim 15, wherein the integration constant is derived from the input signal with subtraction of the weighted output signal of the first integrator stage of the charge storage or charge summation circuit or of a separate integrator circuit with the same function, plus a constant term.

Claim 22

Analog to digital converter according to claim 14, wherein the convergence accelerating signals applied to the comparator input during the time interval of down-integration with the reference current/voltage connected at the beginning of the sub-measurement, is proportional to a polynomial in t, t being the time elapse since the beginning of the sub-measurement, and that the polynomial has a zero point close to the time instant of the end of the down-integration and possibly a second zero point at or close to the beginning of the sub-measurement.

Claim 23

Analog to digital converter according to claim 19, wherein the polynomial of the convergence accelerating signals consists of terms which are proportional to (k+i e ) 2 /(2(1+k)) and to -(1+k)t 2 /2.

Claim 24

Analog to digital converter according to claim 19, wherein the polynomial of the convergence accelerating signals consists of terms which are proportional to (k+i e )t n and to -(1+k)t n+1 where n=0,1,2, . . . .

Claim 25

Analog to digital converter according to claim 13 or 14, wherein the convergence accelerating signals are proportional to -(i e +k)t plus an integration constant, in the time interval of the down-integration with the reference current/voltage connected at the beginning of the sub-measurement.

Claim 26

Analog to digital converter according to claim 1, 13 or 14, wherein a final result with high resolution is obtained a) by individual or respectively weighted or unweighted moving addition of the individual results of m (m=1,2,3, . . . ) sub-measurements or b) by processing the results of individual sub-measurements in a cascaded connection of several moving summation generators.

Claim 27

Analog to digital converter according to claim 1, 13 or 14, but wherein every lth sub-measurement (l=1,2,3, . . . ) the down-integration with the reference current connected at the beginning of the sub-measurement is switched off at the same time as the next following change of the comparator output signal or with constant delay time with respect thereto.

Claim 28

Analog to digital converter according to claim 1, 13 or 14, wherein the convergence accelerating signals are superimposed only in every nth sub-measurement (n=1,2,3, . . . ).

Claim 29

Analog to digital converter according to claim 1, 13 or 14, wherein the sub-measurement duration for a sequence of sub-measurements takes fixed predefined values, but the values differ for the individual sub-measurements of this sequence.