US3765012A
Expired / Lapsed
US
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Analog-digital converter utilizing multiple ramp ingegrating techniques
Assignee: Individual
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Filing: 1972-03-22
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Granted: 1973-10-09
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Expires: 1992-03-22
Abstract
Abstract An analog current I1, to be digitized is fed continuously to the input of an integrator. Two pulse counters, serially connected, algebraically count pulses from a pulse generator, the first pulse counter of the two setting, upon overflow, a bistable element to one of its states. The bistable element will remain in the state until either one of two conditions occur: (a) A threshold switch connected to the output of the integrator commutates or (b) the first pulse of the pulse generator, after change-over of the threshold switch occurs. The first condition (a) occurs when the second pulse counter is at a predetermined, for example final state of its count; the second condition (b) occurs in all other cases. In accordance with the state of the threshold switch, the bistable flip-flop circuit permits either a current I2, or a current I3 (the two currents being of opposite polarity) to be applied, simultaneously with the current I1 to the integrator by suitable switches during predetermined time intervals W. The time interval W is defined as the sum of the time intervals occurring between two successive overflow pulses of the second counter, during which I2 is simultaneously integrated with current I1, less the sum of the time intervals during which current I1 is integrated with current I3. A digital value corresponding to the analog value of current I1 is then stored, in the form of pulse counts, in a counter.
Inventors
- 👤 H Grutzediek
- 👤 J Scheerer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 14:00
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/12; H03M1/50; H03M1/52
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
402 words
Analog-digital converter comprising an integrator (10) having an analog input signal (I1, U1) continuously applied to the input thereof and continuously integrating the signal; means applying an auxiliary signal (I2, I3; Ic) to the integrator to cause the integrator to simultaneously integrate both the analog input signal and the auxiliary signal; a threshold switch (16) connected to the output of the integrator and changing state after the integrated output has reached a predetermined value; a pulse generator (17) providing output pulses; a first pulse counter (11), a bistable element (18), and a second pulse counter (12), the first and second pulse counters (11, 12) being connected in series and to the pulse generator to permanently count pulses of the pulse generator and the first pulse counter (11) being connected to set, at each overflow, the bistabLe element (18) into one of its stable states; and a logic network (23) connected to the threshold switch (16), the pulse generator (17), the second counter (12) and connected to and controlling the bistable element (18) to reset to its other stable state by the output from the logic network (23), the logic network (23) providing an output if: a. the threshold switch (16) changes state and the second pulse counter (12) has reached a predetermined count state; or b. in all cases not included in (a), upon occurrence of the first pulse from the pulse generator (17) after a change of state of the threshold switch (16) has occurred; the bistable element (18), when set upon overflow of the first counter (11) connecting said means applying the auxiliary signal to the integrator to provide an integrated representation of said auxiliary signal to the threshold switch (16) during the time interval said bistable element is in its set state; a third pulse counter (13, 22, 26) connected to said pulse generator and counting pulses from said pulse generator and having control connections with said logic network; a pulse count recording means (20) connected to said third pulse counter (13, 22, 26); the logic network providing a further output (c) controlling transfer of the count from said third pulse counter (13, 22, 26) to said pulse count recording means (20) and resetting said third pulse counter (13, 22, 26) during the time intervals corresponding to two successive overflow pulses of the second counter (12) and during simultaneous integration of the analog input signal and said auxiliary signal.
Claim 2
Dependent Claim
402 words
Analog-digital converter comprising an integrator (10) having an analog input signal (I1, U1) continuously applied to the input thereof and continuously integrating the signal; means applying an auxiliary signal (I2, I3; Ic) to the integrator to cause the integrator to simultaneously integrate both the analog input signal and the auxiliary signal; a threshold switch (16) connected to the output of the integrator and changing state after the integrated output has reached a predetermined value; a pulse generator (17) providing output pulses; a first pulse counter (11), a bistable element (18), and a second pulse counter (12), the first and second pulse counters (11, 12) being connected in series and to the pulse generator to permanently count pulses of the pulse generator and the first pulse counter (11) being connected to set, at each overflow, the bistabLe element (18) into one of its stable states; and a logic network (23) connected to the threshold switch (16), the pulse generator (17), the second counter (12) and connected to and controlling the bistable element (18) to reset to its other stable state by the output from the logic network (23), the logic network (23) providing an output if: a. the threshold switch (16) changes state and the second pulse counter (12) has reached a predetermined count state; or b. in all cases not included in (a), upon occurrence of the first pulse from the pulse generator (17) after a change of state of the threshold switch (16) has occurred; the bistable element (18), when set upon overflow of the first counter (11) connecting said means applying the auxiliary signal to the integrator to provide an integrated representation of said auxiliary signal to the threshold switch (16) during the time interval said bistable element is in its set state; a third pulse counter (13, 22, 26) connected to said pulse generator and counting pulses from said pulse generator and having control connections with said logic network; a pulse count recording means (20) connected to said third pulse counter (13, 22, 26); the logic network providing a further output (c) controlling transfer of the count from said third pulse counter (13, 22, 26) to said pulse count recording means (20) and resetting said third pulse counter (13, 22, 26) during the time intervals corresponding to two successive overflow pulses of the second counter (12) and during simultaneous integration of the analog input signal and said auxiliary signal.
Claim 3
Dependent Claim
92 words
Converter according to claim 1, wherein the third pulse counter is a bi-directional counter (13), the auxiliary signal is formed by a pair of currents (I2, I3) of opposite polarity, and said counter counts in forward direction to count the sum of time intervals occurring between two successive overflow pulses of the second counter (12) when the auxiliary signal of one polarity is integrated with the analog input signal, and the counter counting in reverse, subtracting directions when the auxiliary signal of opposite polarity is simultaneously integrated with the analog input signal.
Claim 4
Dependent Claim
65 words
Converter according to claim 2, wherein the auxiliary currents (I2, I3) are of constant and equal value and of opposite polarity; a pair of control switches are provided, each connecting either of the oppositely poled auxiliary signals to the analog input signal, the logic circuit means controlling the closing of the respective control switch in dependence on the sign of the analog input current (I1).
Claim 5
Dependent Claim
29 words
Converter according to claim 3, wherein the control switch interconnecting the auxiliary signal is opened under control of said bistable element (18) upon overflow of the first pulse counter.
Claim 6
Dependent Claim
25 words
Converter according to claim 2, wherein the bi-directional counter is reset for a new measurement upon each overflow pulse of the second pulse counter (12).
Claim 7
Dependent Claim
234 words
Converter according to claim 1, wherein the auxiliary signal comprises a pair of currents (I2, I3) of constant and equal value, and of opposite polarity; and the third counter comprises a bi-directional counter (13) and means applying the pulses from the pulse generator (17) to the bi-directional counter to be summed therein; a pair of switch means (14, 15) selectively connecting one or the other of the pairs of currents (I2, I3), the bi-directional counter being interconnected with said logic network and the count direction being determined by said logic network, said count direction being in forward direction when one of said switch means is closed to provide an auxiliary current of the same polarity as that of said analog input signal, and the bi-directional counter being controlled to count backwards when the auxiliary current being applied to the integrator is of the opposite polarity to that of said analog input signal; means interconnecting the bi-directional counter (13) to erase the counter for a new count measurement upon occurrence of each overflow pulse of the second pulse counter (12); and means reading out the state of the bi-directional counter (13) of a value V at the end of a cycle of said second pulse counter (12) to obtain an output pulse count (V) which is proportional to the value W of the analog-digital signal to store the value of said signal in digital form.
Claim 8
Dependent Claim
94 words
Converter according to claim 1, including a current source (Ic) of substantially constant current, the current source adding the constant current to the analog input signal (Ie) to obtain a composite analog input signal (I1); means controlling said bistable element (18) to set after overflow of pulses of said first pulse counter (11), said bistable element interrupting application of the auxiliary signal (I2), whereby, after several cycles of the second pulse counter (12) the pulses applied to the pulse counter (22) will, upon each reset of the pulse counter, provide for a constant value.
Claim 9
Dependent Claim
164 words
Converter according to claim 7, wherein the additional current (Ic) is so dimensioned with respect to the analog input signal (Ie) that the modified input signal (I1) always has a positive value; the auxiliary signal (I2) always has a negative polarity; and the third pulse counter (22) is a forward-counting pulse counter, connected to said pulse generator (17) and counting the pulses from said pulse generator during the time of simultaneous integration of the derived analog input signal current (I1) and the auxiliary signal current (I2); the third pulse counter (22) being reset under control of overflow of the second counter (12), the count value in said third forward counting pulse counter (22) upon reset being a digital indicated value of the ratio of the analog input signal (Ie) and the auxiliary signal (I2) after a few cycles of counting of the second pulse counter (12); and means recording the pulse count in said third counting counter (22) in the pulse count recording means.
Claim 10
Dependent Claim
106 words
Converter according to claim 8, wherein the means applying an auxiliary signal apply a plurality of auxiliary signals (Ie; -2 Ic; - I2; + I2), the auxiliary signals being selected in accordance with the value of the analog input signal (Ie) to be expected to provide a modified input signal (I1) which will always bear a predetermined relationship in absolute value with respect to at least two of said auxiliary signals, said predetermined relationship providing a direction of integration by said integrator (10) which will always be in a certain, predetermined direction, to permit use of a single forward-counting pulse counter device for said pulse counter.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-10-08 | 1977-04-09 | 1977-10-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-10-08 | 1981-04-09 | 1981-10-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-10-08 | 1985-04-09 | 1985-10-09 | $7700.00 | Window Closed / Lapsed |