Patent US5066612A successfully refreshed from Google Patents.
US5066612A
Expired / Lapsed
US
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Method of forming wiring of a semiconductor device
Assignee: Fujitsu Semiconductor Ltd
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Filing: 1991-01-03
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Granted: 1991-11-19
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Expires: 2011-01-03
Abstract
Abstract In the course of a production of a semiconductor device with a multilayer insulating layer, when a contact hole is opened in the multilayer insulating layer, an insulating layer activating a metal selective vapor-growth appears at the side wall of the contact hole. A thin metal (e.g., tungsten) layer is selectively deposited in the contact hole. In another case, another metal layer appears within the contact hole. An insulating film preventing a metal selective vapor-growth is deposited over the whole surface of the side wall of the contact hole, the metal layer and a top surface of the multilayer insulating layer, and is anisotropically etched to leave a portion of the film lying on the side wall only as a side wall insulating film. The contact hole is completely filled with another metal (tungsten) by a selective vapor-growth method, to flatten an exposed surface, and then a conductor (e.g., aluminum) line layer is formed on the metal layer in the contact hole and the multilayer insulating layer, to thereby complete the wiring structure of the semiconductor device.
Inventors
- 👤 Takayuki Ohba
- 👤 Shinji Miyagaki
- 👤 Tatsushi Hara
- 👤 Kenji Morishita
- 👤 Seiichi Suzuki
- 👤 Seigen Ri
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 15:16
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/01; H10W20/031; H10W20/056; H10W20/057
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
223 words
A method of forming wiring of a semiconductor device, comprising the following steps (a) to (f): (a) forming a multilayer insulating layer (12) comprising at least an insulating layer (12c) activating a metal selective vapor-growth and a top insulating layer (12d) preventing a metal selective-growth on a semiconductor substrate (1); (b) forming a contact-hole (13) reaching said semiconductor substrate (1) by selectively etching said multilayer insulating layer (12); (c) growing a first metal layer (14) having a thickness such that a surface of the layer (14) is lower than the level of said insulating layer (12c) preventing a metal selective vapor-growth in said contact-hole (13) by a selective vapor-growing method; (d) forming an insulator side film (15a) on the side wall of said contact-hole (13) by depositing an insulator film (15) preventing a metal selective vapor-growth over a whole surface of the inside surface of said contact-hole (13) and said top insulating layer (12d) and by anisotropically etching the film (15) to expose the surface of said first metal layer (14); (e) filling said contact-hole (13) with a second metal layer (16) by depositing said second metal layer (16) on said first metal layer and within said contact-hole by a selective vapor-growing method; and (f) forming a conductor line layer (17) on said second metal layer (16) and said top insulating layer (12d).
Claim 2
Independent Claim
223 words
A method of forming wiring of a semiconductor device, comprising the following steps (a) to (f): (a) forming a multilayer insulating layer (12) comprising at least an insulating layer (12c) activating a metal selective vapor-growth and a top insulating layer (12d) preventing a metal selective-growth on a semiconductor substrate (1); (b) forming a contact-hole (13) reaching said semiconductor substrate (1) by selectively etching said multilayer insulating layer (12); (c) growing a first metal layer (14) having a thickness such that a surface of the layer (14) is lower than the level of said insulating layer (12c) preventing a metal selective vapor-growth in said contact-hole (13) by a selective vapor-growing method; (d) forming an insulator side film (15a) on the side wall of said contact-hole (13) by depositing an insulator film (15) preventing a metal selective vapor-growth over a whole surface of the inside surface of said contact-hole (13) and said top insulating layer (12d) and by anisotropically etching the film (15) to expose the surface of said first metal layer (14); (e) filling said contact-hole (13) with a second metal layer (16) by depositing said second metal layer (16) on said first metal layer and within said contact-hole by a selective vapor-growing method; and (f) forming a conductor line layer (17) on said second metal layer (16) and said top insulating layer (12d).
Claim 3
Dependent Claim
31 words
A method according to claim 1, wherein said insulating layer (12c) activating a metal selective vapor-growth is selected from the group consisting of SiO 2 , SOG, silicon nitride and polyimide.
Claim 4
Dependent Claim
30 words
A method according to claim 1, wherein said top insulating layer (12d) preventing a metal selective-growth is selected from the group consisting of PSG, BSG, BPSG, SiO 2 and SiN.
Claim 5
Dependent Claim
29 words
A method according to claim 1, wherein said insulator film (15) preventing a metal selective-growth is selected from the group consisting of PSG, BSG, BPSG, SiO 2 and SiN.
Claim 6
Dependent Claim
35 words
A method according to claim 1, wherein said first metal layer (14) and second metal layer (16) are selected from the group consisting of tungsten, aluminum, copper, tantalum, molybdenum and silicides of these metals, respectively.
Claim 7
Independent Claim
233 words
A method of forming wiring of a semiconductor device, comprising the following steps (g) to (n): (g) forming a first insulating layer (12a) on a semiconductor substrate (11); (h) forming a first contact-hole by selectively etching said first insulating layer (22a) to expose said semiconductor substrate (21); (i) forming a first metal layer (24) to fill said first contact-hole; (j) forming a multilayer insulating layer comprising at least an insulating layer (22c) activating a metal selective vapor-growth and a top insulating layer (22d) preventing a metal selective-growth, on said first insulating layer (22a) and first metal layer (24); (k) forming a second contact-hole (23) reaching said first metal layer (24) by selectively etching said multilayer insulating layer (22); (1) forming an insulator side film (25a) on the side wall of said contact-hole (23) by depositing an insulator film (25) preventing a metal selective vapor-growth over a whole surface of the inside surface of said second contact-hole (23) and said top insulating layer (22d) and by anisotropically etching the film (25) to expose the surface of said first metal layer (24); (m) filling said contact-hole (23) with a second metal layer (26) by depositing said second metal layer (26) on said first metal layer and within said second contact-hole by a selective vapor-growing method; and (n) forming a conductor line layer (27) on said second metal layer (26) and said top insulating layer (22d).
Claim 8
Independent Claim
233 words
A method of forming wiring of a semiconductor device, comprising the following steps (g) to (n): (g) forming a first insulating layer (12a) on a semiconductor substrate (11); (h) forming a first contact-hole by selectively etching said first insulating layer (22a) to expose said semiconductor substrate (21); (i) forming a first metal layer (24) to fill said first contact-hole; (j) forming a multilayer insulating layer comprising at least an insulating layer (22c) activating a metal selective vapor-growth and a top insulating layer (22d) preventing a metal selective-growth, on said first insulating layer (22a) and first metal layer (24); (k) forming a second contact-hole (23) reaching said first metal layer (24) by selectively etching said multilayer insulating layer (22); (1) forming an insulator side film (25a) on the side wall of said contact-hole (23) by depositing an insulator film (25) preventing a metal selective vapor-growth over a whole surface of the inside surface of said second contact-hole (23) and said top insulating layer (22d) and by anisotropically etching the film (25) to expose the surface of said first metal layer (24); (m) filling said contact-hole (23) with a second metal layer (26) by depositing said second metal layer (26) on said first metal layer and within said second contact-hole by a selective vapor-growing method; and (n) forming a conductor line layer (27) on said second metal layer (26) and said top insulating layer (22d).
Claim 9
Dependent Claim
31 words
A method according to claim 6, wherein said insulating layer (22c) activating a metal selective vapor-growth is selected from the group consisting of SiO 2 , SOG, silicon nitride and polyimide.
Claim 10
Dependent Claim
30 words
A method according to claim 6, wherein said top insulating layer (22d) preventing a metal selective-growth is selected from the group consisting of PSG, BSG, BPSG, SiO 2 and SiN.
Claim 11
Dependent Claim
29 words
A method according to claim 6, wherein said insulator film (25) preventing a metal selective-growth is selected from the group consisting of PSG, BSG, BPSG, SiO 2 and SiN.
Claim 12
Dependent Claim
35 words
A method according to claim 6, wherein said first metal layer (24) and second metal layer (26) are selected from the group consisting of tungsten, aluminum, copper, tantalum, molybdenum and silicide of these metals, respectively.
Claim 13
Independent Claim
206 words
A method of forming wiring of a semiconductor device, comprising the following steps (o) to (s): (o) forming a multilayer insulating layer (34) comprising at least an insulating layer (34b) activating a metal selective vapor-growth and a top insulating layer (34c) preventing a metal selective-growth, over a whole exposed surface of an insulating film (32) on a semiconductor substrate (31) and a first conductor line layer (33) which is formed on said insulating film (32); (p) forming a contact-hole (35) reaching said first conductor line (33) by selectively etching said multilayer insulating layer (34); (q) forming an insulator side film (36) on the side wall of said contact-hole (35) by depositing an insulator film preventing a metal selective vapor-growth over a whole surface of the inside surface of said contact-hole (35) and said top insulating layer (34c) and by anisotropically etching the insulator film to expose the surface of said first conductor line layer (33); (r) filling said contact-hole (35) with a metal layer (37) by depositing said metal layer (37) on said first conductor line layer and within said contact-hole by a selective vapor-growing method; and (s) forming a second conductor line layer (38) on said metal layer (37) and said top insulating layer (34c).
Claim 14
Independent Claim
206 words
A method of forming wiring of a semiconductor device, comprising the following steps (o) to (s): (o) forming a multilayer insulating layer (34) comprising at least an insulating layer (34b) activating a metal selective vapor-growth and a top insulating layer (34c) preventing a metal selective-growth, over a whole exposed surface of an insulating film (32) on a semiconductor substrate (31) and a first conductor line layer (33) which is formed on said insulating film (32); (p) forming a contact-hole (35) reaching said first conductor line (33) by selectively etching said multilayer insulating layer (34); (q) forming an insulator side film (36) on the side wall of said contact-hole (35) by depositing an insulator film preventing a metal selective vapor-growth over a whole surface of the inside surface of said contact-hole (35) and said top insulating layer (34c) and by anisotropically etching the insulator film to expose the surface of said first conductor line layer (33); (r) filling said contact-hole (35) with a metal layer (37) by depositing said metal layer (37) on said first conductor line layer and within said contact-hole by a selective vapor-growing method; and (s) forming a second conductor line layer (38) on said metal layer (37) and said top insulating layer (34c).
Claim 15
Dependent Claim
31 words
A method according to claim 11, wherein said insulating layer (34b) activating a metal selective vapor-growth is selected from the group consisting of SiO 2 , SOG, silicon nitride and polyimide.
Claim 16
Dependent Claim
30 words
A method according to claim 11, wherein said top insulating layer (34c) preventing a metal selective-growth is selected from the group consisting of PSG, BSG, BPSG, SiO 2 and SiN.
Claim 17
Dependent Claim
28 words
A method according to claim 11, wherein said insulator film preventing a metal selective-growth is selected from the group consisting of PSG, BSG, BPSG, SiO 2 and SiN.
Claim 18
Dependent Claim
28 words
A method according to claim 11, wherein said metal layer (37) is selected from the group consisting of tungsten, aluminum, copper, tantalum, molybdenum and silicide of these metals.
Claim 19
Dependent Claim
34 words
A method according to claim 11, wherein said first conductor line layer (33) is a conductor selected from the group consisting of aluminum, tungsten, titanium, metal silicide, titanium nitride, tantalum, molybdenum, zirconium and gold.
References Cited (Backward Citations)
JPS6412551A
Cited
JPS6482653A
Cited
JPH0192137A
Cited
US4948755A
Cited
US4963511A
Cited
US4987099A
Cited
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1994-11-18 | 1995-05-20 | 1995-11-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-11-18 | 1999-05-20 | 1999-11-19 | $3760.00 | Window Closed / Lapsed |
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