Patent US5065413A successfully refreshed from Google Patents.
US5065413A
Expired / Lapsed
US
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Phase locked loop circuit
Assignee: Sony Corp
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Filing: 1990-10-22
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Granted: 1991-11-12
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Expires: 2010-10-22
Abstract
Abstract A phase locked loop circuit is arranged such that the frequency of an input reference clock signal is selected on the basis of a first or second transmission rate of an incoming digital signal, whereby an output digital signal correctly synchronized with the incoming digital signal having the first or second transmission rate can be transmitted. Also, the phase locked loop circuit is arranged so that a first or second central frequency value and a first or second boundary frequency value are set in response to the first or second transmission rate of the incoming digital signal so that, if a frequency value of an output digital signal lies outside of a range of the first or second boundary frequency values, the frequency of the output digital signal is set to the first or second central frequency values. Thus, the phase locked loop circuit of the invention can deliver the output digital signal correctly synchronized with the incoming digital signal having the first or second transmission rate.
Inventors
- 👤 Shinichi Fukuda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 14:04
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/10; G; G11; G11B; G11B20/00; G11B20/10; G11B20/14; G11B20/1403; G11B2020/1087
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
98 words
A phase locked loop circuit in of the type which includes means for detecting a phase error between a reproduced input digital signal having a first or second transmission rate and an output digital signal on the basis of an input reference clock signal and means for controlling the frequency of the output digital signal in response to the phase error, wherein the phase locked loop circuit is characterized by means responsive to the firs or second transmission rate of the input digital signal for selectively controlling the frequency of the input reference clock signal in response thereto.
Claim 2
Dependent Claim
98 words
A phase locked loop circuit in of the type which includes means for detecting a phase error between a reproduced input digital signal having a first or second transmission rate and an output digital signal on the basis of an input reference clock signal and means for controlling the frequency of the output digital signal in response to the phase error, wherein the phase locked loop circuit is characterized by means responsive to the firs or second transmission rate of the input digital signal for selectively controlling the frequency of the input reference clock signal in response thereto.
Claim 3
Dependent Claim
185 words
A phase locked loop circuit comprising a) phase comparator means for detecting a phase error between a reproduced input digital signal having a first or second transition rate and an output digital signal and for controlling the frequency of the output digital signal in response to the phase error; b) lock range setting means for setting a first or second central frequency value and a first or second boundary frequency value in response to the first or second transmission rate; c) lock range determining means for determining whether or not the frequency value of the output digital signal falls within the range of the first or second boundary frequency values set by the lock range setting means; and d) frequency setting means for controlling the phase comparator means to cause the output digital signal to have a frequency corresponding to the first or second central frequency values determined by the lock range setting means on the basis of determined result of the lock range determining means if the frequency value of the output digital signal lies outside of the first or second boundary frequency values.
Claim 4
Dependent Claim
185 words
A phase locked loop circuit comprising a) phase comparator means for detecting a phase error between a reproduced input digital signal having a first or second transition rate and an output digital signal and for controlling the frequency of the output digital signal in response to the phase error; b) lock range setting means for setting a first or second central frequency value and a first or second boundary frequency value in response to the first or second transmission rate; c) lock range determining means for determining whether or not the frequency value of the output digital signal falls within the range of the first or second boundary frequency values set by the lock range setting means; and d) frequency setting means for controlling the phase comparator means to cause the output digital signal to have a frequency corresponding to the first or second central frequency values determined by the lock range setting means on the basis of determined result of the lock range determining means if the frequency value of the output digital signal lies outside of the first or second boundary frequency values.
Claim 5
Dependent Claim
105 words
A phase locked loop method comprising the steps of detecting the phase error between a reproduced input digital signal having a first or second transmission rate and an output digital signal on the basis of an input reference clock signal and controlling the frequency of the output digital signal in response to the phase error, wherein the phase locked loop method is characterized by the steps of: detecting which of the first or the second transmission rates the input digital signal has; and selectively controlling the frequency of the input reference clock signal in response to the detected transmission rate of the input digital signal.
Claim 6
Dependent Claim
105 words
A phase locked loop method comprising the steps of detecting the phase error between a reproduced input digital signal having a first or second transmission rate and an output digital signal on the basis of an input reference clock signal and controlling the frequency of the output digital signal in response to the phase error, wherein the phase locked loop method is characterized by the steps of: detecting which of the first or the second transmission rates the input digital signal has; and selectively controlling the frequency of the input reference clock signal in response to the detected transmission rate of the input digital signal.
Claim 7
Dependent Claim
152 words
A phase locked loop method comprising the steps of detecting the phase error between a reproduced input digital signal having a first or second transmission rate and an output digital signal and controlling the frequency of the output digital signal in response to the phase error, wherein the phase locked loop method comprises the steps of: a) setting a first or second central frequency value and a first or second boundary frequency value in response to the first or second transmission rate; b) determining whether or not the frequency value of the output digital signal falls within the range of the first or second boundary frequency values set by the preceding step; and c) controlling the output digital signal to have a frequency corresponding to the first or the second central frequency values if the frequency value of the output digital signal lies outside of the first or second boundary frequency values.
Claim 8
Dependent Claim
152 words
A phase locked loop method comprising the steps of detecting the phase error between a reproduced input digital signal having a first or second transmission rate and an output digital signal and controlling the frequency of the output digital signal in response to the phase error, wherein the phase locked loop method comprises the steps of: a) setting a first or second central frequency value and a first or second boundary frequency value in response to the first or second transmission rate; b) determining whether or not the frequency value of the output digital signal falls within the range of the first or second boundary frequency values set by the preceding step; and c) controlling the output digital signal to have a frequency corresponding to the first or the second central frequency values if the frequency value of the output digital signal lies outside of the first or second boundary frequency values.
Claim 9
Dependent Claim
163 words
A phase locked loop circuit comprising: phase comparator means for detecting the phase difference between a reproduced digital signal having a first or second transmission rate and an output digital signal and for controlling the frequency of the output digital signal in response to the phase error, the phases comparator means carrying out the detecting and output digital signal frequency controlling operations at the timing of a master reference clock signal; master clock signal generating means for generating master clock signals at first and second frequencies corresponding to the first and second transmission rates of the reproduced digital signal; means for detecting the transmission rate of the reproduced digital signal and selectively supplying to the phase comparator means as the master reference clock signals the master clock signals at the first frequency when the reproduced digital signal has the first transmission rate and for supplying the master clock signals at the second frequency when the reproduced digital signal has the second transmission rate.
Claim 10
Dependent Claim
163 words
A phase locked loop circuit comprising: phase comparator means for detecting the phase difference between a reproduced digital signal having a first or second transmission rate and an output digital signal and for controlling the frequency of the output digital signal in response to the phase error, the phases comparator means carrying out the detecting and output digital signal frequency controlling operations at the timing of a master reference clock signal; master clock signal generating means for generating master clock signals at first and second frequencies corresponding to the first and second transmission rates of the reproduced digital signal; means for detecting the transmission rate of the reproduced digital signal and selectively supplying to the phase comparator means as the master reference clock signals the master clock signals at the first frequency when the reproduced digital signal has the first transmission rate and for supplying the master clock signals at the second frequency when the reproduced digital signal has the second transmission rate.
Claim 11
Dependent Claim
151 words
A phase locked loop method comprising the steps of: (a) detecting the phase difference between a reproduced digital signal having a first or second transmission rate and an output digital signal and for controlling the frequency of the output digital signal in response to the phase error, wherein the detecting and output digital signal frequency controlling operations are carried out at the timing of a master reference clock signal; (b) generating master clock signals at first and second frequencies corresponding to the first and second transmission rates of the reproduced digital signal; (c) detecting the transmission rate of the reproduced digital signal and selectively using as the master reference clock signals in step (a) the master clock signals at the first frequency when the reproduced digital signal has the first transmission rate and the master clock signals at the second frequency when the reproduced digital signal has the second transmission rate.
Claim 12
Dependent Claim
151 words
A phase locked loop method comprising the steps of: (a) detecting the phase difference between a reproduced digital signal having a first or second transmission rate and an output digital signal and for controlling the frequency of the output digital signal in response to the phase error, wherein the detecting and output digital signal frequency controlling operations are carried out at the timing of a master reference clock signal; (b) generating master clock signals at first and second frequencies corresponding to the first and second transmission rates of the reproduced digital signal; (c) detecting the transmission rate of the reproduced digital signal and selectively using as the master reference clock signals in step (a) the master clock signals at the first frequency when the reproduced digital signal has the first transmission rate and the master clock signals at the second frequency when the reproduced digital signal has the second transmission rate.
References Cited (Backward Citations)
US4375693A
Cited
US4534044A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-11-11 | 1995-05-13 | 1995-11-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-11-11 | 1999-05-13 | 1999-11-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-11-11 | 2003-05-13 | 2003-11-12 | $7700.00 | Window Closed / Lapsed |