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US5065384A
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Clock signal generating circuit for a data storing and reproducing system
Assignee: Pioneer Corp
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Filing: 1988-12-05
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Granted: 1991-11-12
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Expires: 2008-12-05
Abstract
Abstract A clock signal producing circuit for a data storing and reproducing system in which a reference clock signal having a predetermined frequency is generated, a first sync-signal detection signal is generated when the time between two adjacent pulses in the input signal which is measured by the reference clock signal becomes equal to the predetermined reference value, the clock edge pulse is separated from the input signal using the first sync-signal detection signal and then outputted, and a reproducing clock signal having a predetermined frequency coinciding with the generating timing of the separated clock edge pulse is generated.
Inventors
- 👤 Fumihiko Yokogawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 20:47
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; G11B20/14; G11B20/1403; G11B27/00; G11B27/10; G11B27/19; G11B27/28; G11B27/30; G11B27/3027; G11B27/36; H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/085; H03L7/087; H03L7/095; G11B20/18; G11B20/1879
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
182 words
A clock signal generating circuit for generating a clock signal for use in a data storage and reproduction system, said clock signal having a predetermined frequency in synchronism with clock edge pulses each of which exists at a predetermined location in a sync-signal section having a predetermined length between two adjacent pulses thereof, said clock signal generating circuit comprising: a first clock signal generating means for generating a reference clock signal having a predetermined frequency; a first synchronism detection means for measuring a time period between the two adjacent pulses in an input signal on the basis of said reference clock signal for said time period and outputting a first syncsignal detection signal when said measured time period is equal to a predetermined value; a separation means for separating said clock edge pulses in said input signal in response to said first sync-signal detection signal, and outputting said clock edge pulses; and a second clock signal generating means for generating a reproducing clock signal having a predetermined frequency in synchronism with said clock edge pulses which are outputted from said separation means.
Claim 2
Dependent Claim
182 words
A clock signal generating circuit for generating a clock signal for use in a data storage and reproduction system, said clock signal having a predetermined frequency in synchronism with clock edge pulses each of which exists at a predetermined location in a sync-signal section having a predetermined length between two adjacent pulses thereof, said clock signal generating circuit comprising: a first clock signal generating means for generating a reference clock signal having a predetermined frequency; a first synchronism detection means for measuring a time period between the two adjacent pulses in an input signal on the basis of said reference clock signal for said time period and outputting a first syncsignal detection signal when said measured time period is equal to a predetermined value; a separation means for separating said clock edge pulses in said input signal in response to said first sync-signal detection signal, and outputting said clock edge pulses; and a second clock signal generating means for generating a reproducing clock signal having a predetermined frequency in synchronism with said clock edge pulses which are outputted from said separation means.
Claim 3
Dependent Claim
98 words
A clock signal generating circuit for a data storage and reproduction system according to claim 1, wherein said second clock generating means comprises: a phase locked loop circuit comprising a phase comparator circuit which compares a phase of said clock edge pulse with a phase of said reproducing clock signal having a frequency different from said clock edge pulse; a frequency control circuit which controls the frequency of said reproducing clock signal by supplying said phase locked loop circuit with a signal corresponding to a value obtained from measurement of a time period between adjacent clock edge pulses.
Claim 4
Dependent Claim
95 words
A clock signal generating circuit for a data storage and reproduction system according to claim 1, wherein said separation means comprises: means for generating a second sync-signal detection signal when measurement of said time period between two adjacent pulses in an input signal by said reproducing clock; means for generating a synchronism completion signal when said second sync-signal detection signal is generated successively at a predetermined interval; and said separation means separating and outputting the clock edge pulse from said input signal by said second sync-signal detection signal when said synchronism completion signal is present.
References Cited (Backward Citations)
US4596963A
Cited
US4872155A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-11-11 | 1995-05-13 | 1995-11-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-11-11 | 1999-05-13 | 1999-11-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-11-11 | 2003-05-13 | 2003-11-12 | $7700.00 | Window Closed / Lapsed |