US4872155A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Clock generator circuit and a synchronizing signal detection method in a sampled format system and a phase comparator circuit suited for generation of the clock
Assignee: Pioneer Corp
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Filing: 1988-03-01
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Granted: 1989-10-03
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Expires: 2008-03-01
Abstract
Abstract A recording-reproducing clock generator circuit generates a reproduced clock having a predetermined frequency from a read out signal including such pulses that the interval between two successive pulses thereof at a predetermined length is to be used as a synchronizing signal region. The circuit generates a reference clock of a predetermined frequency, generates a first sync signal detection signal when the distance between two successive pulses in the input signal measured by means of the clock pulses is equal to a predetermined reference value, separates a clock edge pulse from the input signal by using the first sync signal detection signal, and generates the reproduced clock having the predetermined frequency and synchronized with the separated clock edge pulse.
Inventors
- 👤 Fumihiko Yokogawa
- 👤 Hiroyuki Hirano
- 👤 Keiji Kinpara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 22:33
CPC Classifications
G; G11; G11B; G11B27/00; G11B27/36; G11B20/00; G11B20/10; G11B20/14; G11B20/1403; G11B27/10; G11B27/19; G11B27/28; G11B27/30; G11B27/3027; H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/085; H03L7/087; H03L7/095; G11B20/18; G11B20/1879
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
173 words
A recording-reproducing clock generator circuit for generating a reproduced clock having a predetermined frequency from a read out signal which includes such pulses that the interval between two successive pulse thereof at a predetermined length is to be used as a synchronizing signal region, said reproduced clock signal synchronized with clock edge pulses located at predetermined positions with reference to said synchronizing signal region, said recording-reproducing clock generator circuit comprising: first clock generator means for generating a reference clock at a predetermined frequency; first sync detector means for generating a first sync signal detection signal when a value obtained by measuring the distance between two successive pulses in the input signal by means of said reference clock is equal to a predetermined value; separating means for separating the clock edge pulses from the input signal according to said first sync signal detection signal and outputting the pulses; and second clock generator means for generating a reproduced clock having the predetermined frequency in synchronism with said clock edge pulses outputted from said separating means.
Claim 2
Dependent Claim
173 words
A recording-reproducing clock generator circuit for generating a reproduced clock having a predetermined frequency from a read out signal which includes such pulses that the interval between two successive pulse thereof at a predetermined length is to be used as a synchronizing signal region, said reproduced clock signal synchronized with clock edge pulses located at predetermined positions with reference to said synchronizing signal region, said recording-reproducing clock generator circuit comprising: first clock generator means for generating a reference clock at a predetermined frequency; first sync detector means for generating a first sync signal detection signal when a value obtained by measuring the distance between two successive pulses in the input signal by means of said reference clock is equal to a predetermined value; separating means for separating the clock edge pulses from the input signal according to said first sync signal detection signal and outputting the pulses; and second clock generator means for generating a reproduced clock having the predetermined frequency in synchronism with said clock edge pulses outputted from said separating means.
Claim 3
Dependent Claim
93 words
A recording-reproducing clock generator circuit as set forth in claim 1, wherein said second clock generator means comprises a phase locked loop circuit including; a phase comparator circuit for comparing phases of said clock edge pulses and said reproduced clock having a frequency different from frequency of said clock edge pulse, and a frequency control circuit for controlling the frequency of said reproduced clock by supplying said phase locked loop circuit with a signal corresponding to the value of the distance between said clock edge pulses measured by means of said reproduced clock.
Claim 4
Dependent Claim
116 words
A recording-reproducing clock generator circuit as set forth in claim 1, wherein said separating means comprises; means for generating a second sync signal detection signal when the value of the distance between two successive pulses in the input signal measured by means of said reproduced clock is equal to a predetermined value, and means for generating a synchronization completion signal when said second sync signal detection signals are generated a predetermined number of times in succession at intervals of a predetermined distance, and wherein said separating means is adapted such that, while said synchronization completion signal is existing, the clock edge pulses are separated from the input signal according to said second sync signal detection signal.
References Cited (Backward Citations)
US4713802A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-10-02 | 1993-04-03 | 1993-10-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-10-02 | 1997-04-03 | 1997-10-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-10-02 | 2001-04-03 | 2001-10-03 | $7700.00 | Window Closed / Lapsed |