Phase-locked loop bandwidth switching demodulator for suppressed carrier signals

Claim 2

A receiver for tracking a carrier suppressed phase-shifted input signal comprising: (a) a phase-locked loop circuit for receiving said input signal and having a variable frequency oscillator responsive to a control signal for oscillating at a frequency corresponding to an intermediate frequency and a frequency difference detector for producing an output signal indicative of the frequency difference between the frequency of said input signal and said intermediate frequency; (b) a feedback loop network having a narrow-band path and a wide-band path and being responsive to said detector output signal for producing said control signal and applying said control signal to said oscillator through one of said paths whereby to change the intermediate frequency of said oscillator in response to said control signal; (c) a quality detector responsive to said detector output signal for producing a signal corresponding to the bit error rate of said input signal; and (d) selection means responsive to said bit error rate signal for causing said control signal to pass through said narrow-band path when said bit error rate signal is below a predetermined threshold and through said wide-band path when said bit error rate signal exceeds said predetermined threshold.

Claim 3

A receiver as claimed in claim 1 wherein said circuit comprises a Costas loop demodulator.

Claim 4

A receiver as claimed in claim 1 wherein said quality detector comprises: a received signal decoder for processing encoded binary data according to an error correction scheme; a bit error signalling means for producing a signal corresponding to a detected bit error; a first counter for counting bit errors over a block of received bits; a second counter for counting bit errors over a second block of received bits where said second block of received bits is larger than said first block of bits; means for producing a received data quality signal corresponding to the bit counts of said first and second counters.

Claim 5

A receiver as claimed in claim 3 wherein said first block of bits is at least 1024 bits and said second block of bits is at least 5 times the number of bits contained in said first block.

Claim 6

A receiver as claimed in claim 3 wherein said error correction scheme is convolution encoding with Viterbi decoding.

Claim 7

A receiver as claimed in claim 2 wherein said quality detector comprises: a received signal decoder for processing encoded binary data according to an error correction scheme; a bit error signalling means for producing a signal corresponding to a detected bit error; a first counter for counting bit errors over a block of received bits; a second counter for counting bit errors over a second block of received bits where said second block of received bits is larger than said first block of bits; means for producing a received data quality signal corresponding to the bit counts of said first and second counters.

Claim 8

A receiver as claimed in claim 6 wherein said first block of bits is at least 1024 bits and said second block of bits is at least 5 times the number of bits contained in said first block.

Claim 9

A receiver as claimed in claim 7 wherein said error correction scheme is convolution encoding with Viterbi decoding.

Claim 10

A receiver for tracking a carrier suppressed phase-shifted input signal comprising: (a) a phase-locked loop circuit for receiving said input signal and having a variable frequency oscillator responsive to a control signal for oscillating at a frequency corresponding to an intermediate frequency and a frequency difference detector for producing an output signal indicative of the frequency difference between the frequency of said input signal and said intermediate frequency; (b) a feedback loop network having a narrow-band path and a wide-band path and being responsive to said detector output signal for producing said control signal and applying said control signal to said oscillator through one of said paths whereby to change the intermediate frequency of said oscillator in response to said control signal; (c) a quality detector responsive to said detector output signal for producing a signal corresponding to the bit error rate of said input signal having: a signal decoder for processing encoded binary data according to an error correction scheme; bit error signalling means for producing a signal corresponding to a detected bit error; a first counter for counting bit errors over a first block of received bits; a second counter for counting bit errors over a second block of received bits where said second block of received bits is larger than said first block of bits; and means responsive to the bit counts of said first and second counters for producing a received data quality signal; and (d) selection means responsive to said received data quality signal for causing said control signal to pass through said narrow-band path when said bit error rate signal is below a predetermined threshold and through said wide-band path when said bit error rate signal exceeds said predetermined threshold.

Claim 11

A receiver for tracking a carrier suppressed phase-shifted input signal comprising: (a) a phase-locked loop circuit for receiving said input signal and having a variable frequency oscillator responsive to a control signal for oscillating at a frequency corresponding to an intermediate frequency and a frequency difference detector for producing an output signal indicative of the frequency difference between the frequency of said input signal and said intermediate frequency; (b) a feedback loop network having a narrow-band path and a wide-band path and being responsive to said detector output signal for producing said control signal and applying said control signal to said oscillator through one of said paths whereby to change the intermediate frequency of said oscillator in response to said control signal; (c) a quality detector responsive to said detector output signal for producing a signal corresponding to the bit error rate of said input signal having: a signal decoder for processing encoded binary data according to an error correction scheme; bit error signalling means for producing a signal corresponding to a detected bit error; a first counter for counting bit errors over a first block of received bits; a second counter for counting bit errors over a second block of received bits where said second block of received bits is larger than said first block of bits; and means responsive to the bit counts of said first and second counters for producing a received data quality signal; and (d) selection means responsive to said received data quality signal for causing said control signal to pass through said narrow-band path when said bit error rate signal is below a predetermined threshold and through said wide-band path when said bit error rate signal exceeds said predetermined threshold.

Claim 12

A receiver as claimed in claim 9 wherein said circuit comprises a Costas loop demodulator.

Claim 13

A receiver as claimed in claim 9 wherein said first block of bits is at least 1024 bits and said second block of bits is at least 5 times the number of bits contained in said first block.

Claim 14

A receiver as claimed in claim 9 wherein said error correction scheme is convolution encoding with Viterbi decoding.

Claim 15

A receiver as claimed in claim 10 wherein said first block of bits is at least 1024 bits and said second block of bits is at least 5 times the number of bits contained in said first block.

Claim 16

A receiver as claimed in claim 13 wherein said error correction scheme is convolution encoding with Viterbi decoding.

Claim 17

A receiver as claimed in claim 10 wherein said error correction scheme is convolution encoding with Viterbi decoding.

Claim 20

A method of communicating digitally encoded information by carrier suppressed electromagnetic transmission as claimed in claim 16 wherein the encoding algorithm is forward error correction.

Claim 21

A method of communicating digitally encoded information by carrier suppressed electromagnetic transmission as claimed in claim 16 wherein the encoding algorithm is convolution encoding.

Claim 22

A method of communicating digitally encoded information by carrier suppressed electromagnetic transmission as claimed in claim 16 wherein the decoding algorithm is viterbi decoding.

Claim 23

A method of communicating digitally encoded information by carrier suppressed electromagnetic transmission as claimed in claim 17 wherein the encoding algorithm is convolution encoding.

Claim 24

A method of communicating digitally encoded information by carrier suppressed electromagnetic transmission as claimed in claim 20 wherein the decoding algorithm is viterbi decoding.

Claim 25

A method of communicating digitally encoded information by carrier suppressed electromagnetic transmission as claimed in claim 17 wherein the decoding algorithm is viterbi decoding.

Claim 26

A method of communicating digitally encoded information by carrier suppressed electromagnetic transmission as claimed in claim 18 wherein the decoding algorithm is viterbi decoding.