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US5063565A
Expired / Lapsed
US
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Single-error detecting and correcting system
Assignee: Toshiba Corp
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Filing: 1991-04-23
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Granted: 1991-11-05
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Expires: 2011-04-23
Abstract
Abstract A single-error detecting and correcting system includes a first memory for storing data and outputting the stored data in response to an input address applied, the data having control data and error check data, and an error detector for checking in accordance with the check data whether the control data in data read from the first memory is in error and generating an error detect signal in accordance with the result of the error checking. An error corrector has a second memory for storing correction data and responds to the errror detect signal to correct the data read from the first memory in accordance with the correction data, to set the first memory to a write mode and to write the corrected data into the first memory.
Inventors
- 👤 Takayoshi Ohashi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 19:06
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1076; G06F11/22; G06F11/26; G06F11/273; G06F11/2736
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
141 words
A system for detecting and correcting single-bit error, comprising: first storage means for storing data and outputting the data in response to an input address in a read mode, the data comprising control data and check data; error detecting means for checking in accordance with the check data whether the control data in the data read from said first storage means contains an error and generating an error detect signal in accordance with the result of the error checking; and correcting means, responsive to the error detect signal from said error detecting means and having second storage means for storing a single error correction-double error detection (SEC-DED) code, for correction the data from said first storage means in accordance with the SEC-DED code, setting said first storage means to a write mode and writing corrected data into said first storage means.
Claim 2
Independent Claim
141 words
A system for detecting and correcting single-bit error, comprising: first storage means for storing data and outputting the data in response to an input address in a read mode, the data comprising control data and check data; error detecting means for checking in accordance with the check data whether the control data in the data read from said first storage means contains an error and generating an error detect signal in accordance with the result of the error checking; and correcting means, responsive to the error detect signal from said error detecting means and having second storage means for storing a single error correction-double error detection (SEC-DED) code, for correction the data from said first storage means in accordance with the SEC-DED code, setting said first storage means to a write mode and writing corrected data into said first storage means.
Claim 3
Dependent Claim
52 words
The system according to claim 1, further comprising: clock generating means for selectively generating a clock signal in response to the error detect signal from said error detecting means; and register means for holding the data from said first storage means in response to the clock signal from said clock generating means.
Claim 4
Dependent Claim
54 words
The system according to claim 2, wherein said correcting means further includes means responsive to writing of the corrected data into said first storage means, for setting said first storage means to the read mode, applying the address to said first storage means and causing said clock generating means to generate the clock signal.
Claim 5
Dependent Claim
36 words
The system according to claim 2, wherein said correcting means further includes means for writing the corrected data into said register means in response to the writing of the corrected data into said first storage means.
Claim 6
Dependent Claim
92 words
The system according to claim 1, further comprising: selecting means responsive to an input select control signal, for selecting one of a first address applied thereto and a second address from said correcting means and applying the selected address as the address to said first storage means, and wherein said correcting mean includes means for receiving the address from said selecting means and applying the received address to said selector means as the second address and applying the select control signal to said selecting means in response to the error detect signal.
Claim 7
Dependent Claim
21 words
The system according to claim 5, further comprising: microsequencer means responsive to an input operation initiating command for applying the first
Claim 8
Independent Claim
88 words
A method of detecting and correcting a single-bit error, comprising: generating data stored in a first memory, in accordance with a memory address in a read mode, the data comprising control data and check data; checking whether the control data contains an error in accordance with the check data; generating an error detect signal in accordance with the result of the error checking; and correcting the data with a single error correction-double error detection (SEC-DED) code stored in a second memory, in response to the error detect signal.
Claim 9
Independent Claim
88 words
A method of detecting and correcting a single-bit error, comprising: generating data stored in a first memory, in accordance with a memory address in a read mode, the data comprising control data and check data; checking whether the control data contains an error in accordance with the check data; generating an error detect signal in accordance with the result of the error checking; and correcting the data with a single error correction-double error detection (SEC-DED) code stored in a second memory, in response to the error detect signal.
Claim 10
Dependent Claim
30 words
The method according to claim 7, further comprising: holding the data in response to a clock signal; and selectively generating the clock signal in accordance with the error detect signal.
Claim 11
Dependent Claim
16 words
The method according to claim 7, further comprising: writing the corrected data into said first memory.
Claim 12
Independent Claim
146 words
A system for detecting and correcting a single-bit error, comprising: first storage means for storing data and outputting the data in response to an input address in a read mode, the data comprising control data and check data; register means responsive to an input clock signal, for latching the data from aid first storage means; error detecting means for checking in accordance with the check data whether the control data in the data read from said first storage means contains an error and generating an error detect signal in accordance with the result of the error checking; and correcting means having second storage means for storing a single error correction-double error detection (SEC-DED code and responsive to said error detect signal, for correcting the data from said first storage means in accordance with the SEC-DED code and for writing the corrected data into said register means.
Claim 13
Independent Claim
146 words
A system for detecting and correcting a single-bit error, comprising: first storage means for storing data and outputting the data in response to an input address in a read mode, the data comprising control data and check data; register means responsive to an input clock signal, for latching the data from aid first storage means; error detecting means for checking in accordance with the check data whether the control data in the data read from said first storage means contains an error and generating an error detect signal in accordance with the result of the error checking; and correcting means having second storage means for storing a single error correction-double error detection (SEC-DED code and responsive to said error detect signal, for correcting the data from said first storage means in accordance with the SEC-DED code and for writing the corrected data into said register means.
Claim 14
Dependent Claim
82 words
The system according to claim 10, further comprising: clock generating means for generating the clock signal in response to an input start instruction from said correcting means and stopping the generation of the clock signal in response to the error detect signal from said error detecting means, and wherein said correcting means further comprises means responsive to the error detect signal, for generating and applying the start instruction to said clock generating means to write the corrected data into said register means.
Claim 15
Dependent Claim
26 words
The system according to claim 10, further comprising: microsequencer means responsive to an input operation initiating command for applying the address to said first storage means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-11-04 | 1995-05-06 | 1995-11-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-11-04 | 1999-05-06 | 1999-11-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-11-04 | 2003-05-06 | 2003-11-05 | $7700.00 | Window Closed / Lapsed |