Transistor write current switching circuit for magnetic recording

Claim 2

A transistor circuit comprising a current mirror circuit including an input current terminal, a first, second, third and fourth bipolar transistors, and first and second output current terminals; said first bipolar transistor being connected to said input current terminal and a source potential to produce a base current for each of said second, third and fourth bipolar transistors, said second bipolar transistor constituting an input-side transistor connected to said input current terminal, and said third and said fourth bipolar transistor constituting output-side transistors connected to said output current terminals, respectively, and said second, third and fourth bipolar transistors being coupled to a reference potential and supplied with said base current; and an output-side transistor on-off control circuit including first and second MOS transistors connected to the bases of said third and said fourth bipolar transistor for on-off switching of the base currents thereto in response to control signals applied to said first and second MOS transistors through first and second control terminals, respectively.

Claim 3

A transistor circuit according to claim 1, further comprising a third MOS transistor connected between the emitter of said first bipolar transistor and the base of said second bipolar transistor and having its gate connected to a constant operating potential.

Claim 4

A transistor circuit according to claim 1, further comprising an output-side transistor off state ensuring circuit including fourth and fifth MOS transistors connected to said third and said fourth bipolar transistor, respectively, for biasing said output-side bipolar transistors in their off state alternately.

Claim 5

A transistor circuit according to claim 3, wherein said output-side transistor on-off control circuit and said output-side transistor off state ensuring circuit are connected to said first and second control terminals so as to be supplied with on-off signals to said first and second MOS transistors, respectively.

Claim 6

A transistor circuit according to claim 4, wherein said first MOS transistor and said fourth MOS transistor are coupled to said first control terminal at their gates and said second MOS transistor and said fifth MOS transistor are coupled to said second control terminal at their gates, respectively.

Claim 7

A transistor circuit according to claim 5, wherein said first, second, fourth and fifth MOS transistors are of the same conductivity channel type, and first and second invertors are connected between the gate of said fourth MOS transistor and said first control terminal and between the gate of said fifth MOS transistor and said second control terminal, respectively, and the gate of said third MOS transistor is connected to a power supply terminal.

Claim 8

A transistor circuit according to claim 5, wherein said first and second MOS transistors are of a first conductivity channel type and said fourth and fifth MOS transistors are of a second conductivity channel type, and the gates of said fourth MOS transistor and said fifth MOS transistor are connected directly to said first and second control terminal, respectively, and the gate of said third MOS transistor is connected to a ground terminal.

Claim 9

A transistor circuit according to claim 2, wherein said first, second, third and fourth bipolar transistors are of an NPN type, the collectors of said first and second bipolar transistors are connected to a power supply terminal and said input current terminal, respectively, the emitters thereof are connected to a ground terminal through first and second resistors, respectively, the collectors of said third and fourth bipolar transistors are connected to said first and second output current terminals, respectively, and the emitters thereof are connected to said ground terminal through third and fourth resistors, respectively, and the bases of said first and second MOS transistors are connected to first and second control terminals coupled to be supplied with on-off control signals, respectively.

Claim 10

A transistor circuit according to claim 8, further comprising short-circuiting means connected between the base and the emitter of each of said third and fourth bipolar transistors, for short-circuiting said base and the ground terminal in response to the on-off control signal applied to said short-circuiting means to ensure the off state of the corresponding one of said third and fourth bipolar transistors.

Claim 11

A transistor circuit according to claim 2, wherein the ratio between the gate width to gate length value of said third MOS transistor and the gate width to gate length value of said first MOS transistor or said second MOS transistor is equal to an input current to output current ratio.

Claim 12

A transistor circuit comprising a current mirror circuit including an input terminal and output terminals, a ground terminal, an input-side bipolar transistor connected to said input terminal and output-side bipolar transistors connected to said output terminals, a first MOS transistor for supplying a base current to said input-side bipolar transistor and second and third MOS transistors for supplying base currents to said output-side bipolar transistors, fourth and fifth MOS transistors connected between said ground terminal and bases of said output-side bipolar transistors, respectively, a base current generating bipolar transistor having a base connected to said input terminal and a collector connected to a source potential, said input-side bipolar transistor and said output-side bipolar transistors being supplied with respective base currents from a potential point coupled to the emitter of said base current generating bipolar transistor, through said first, second and third MOS transistors, said first MOS transistor being constantly in its on state, said second and fourth MOS transistors being alternately on-off switched, and said third and fifth MOS transistors connected to the other of said output-side bipolar transistors being alternately on-off switched.

Claim 13

A transistor circuit comprising a current mirror circuit including an input terminal and output terminals, a ground terminal, an input-side bipolar transistor connected to said input terminal and output-side bipolar transistors connected to said output terminals, a first MOS transistor for supplying a base current to said input-side bipolar transistor and second and third MOS transistors for supplying base currents to said output-side bipolar transistors, fourth and fifth MOS transistors connected between said ground terminal and bases of said output-side bipolar transistors, respectively, a base current generating bipolar transistor having a base connected to said input terminal and a collector connected to a source potential, said input-side bipolar transistor and said output-side bipolar transistors being supplied with respective base currents from a potential point coupled to the emitter of said base current generating bipolar transistor, through said first, second and third MOS transistors, said first MOS transistor being constantly in its on state, said second and fourth MOS transistors being alternately on-off switched, and said third and fifth MOS transistors connected to the other of said output-side bipolar transistors being alternately on-off switched.

Claim 14

A transistor circuit having an input terminal, a first and a second output terminal, a reference potential terminal, a circuit node and a first and a second control terminal, said circuit comprising: a first, a second and a third transistor each including a first and a second main electrode and a control electrode, the impedance of a current path between said first and said second main electrode being controlled responsive to a control signal applied to said control electrode; a means for having the current path between said first and said second main electrode of said first transistor connected between said input terminal and said reference potential terminal; a means for having said input terminal connected to said circuit node; a means for having said circuit node connected to said control electrode of said first transistor; a means for having the current path between said first and said second main electrode of said second transistor coupled between said first output terminal and said reference potential terminal; a means for having the current path between said first and said second main electrode of said third transistor coupled between said second output terminal and said reference potential terminal; a first switching means connected between said circuit node and said control electrode of said second transistor and to be ON or OFF state in response to the voltage level at said first control terminal; and a second switching means connected between said circuit node and said control electrode of said third transistor and to be ON or OFF state in response to the voltage level at said second control terminal.

Claim 15

A transistor circuit having an input terminal, a first and a second output terminal, a reference potential terminal, a circuit node and a first and a second control terminal, said circuit comprising: a first, a second and a third transistor each including a first and a second main electrode and a control electrode, the impedance of a current path between said first and said second main electrode being controlled responsive to a control signal applied to said control electrode; a means for having the current path between said first and said second main electrode of said first transistor connected between said input terminal and said reference potential terminal; a means for having said input terminal connected to said circuit node; a means for having said circuit node connected to said control electrode of said first transistor; a means for having the current path between said first and said second main electrode of said second transistor coupled between said first output terminal and said reference potential terminal; a means for having the current path between said first and said second main electrode of said third transistor coupled between said second output terminal and said reference potential terminal; a first switching means connected between said circuit node and said control electrode of said second transistor and to be ON or OFF state in response to the voltage level at said first control terminal; and a second switching means connected between said circuit node and said control electrode of said third transistor and to be ON or OFF state in response to the voltage level at said second control terminal.

Claim 16

A transistor circuit according to claim 12, wherein said first, second and third transistors are bipolar transistors, said first and said second main electrode and said control electrode are of a collector, an emitter and a base, respectively, and said first and said second switching means are of an insulated-gate type field effect transistor, respectively.

Claim 17

A transistor circuit according to claim 13, further comprising a source potential terminal and wherein said means for connecting said input terminal to said circuit node includes a fourth bipolar transistor, said fourth transistor having a base and an emitter connected to said input terminal and said circuit node, respectively, and a collector connected to said source potential terminal, and said means for connecting said circuit node to said control electrode of said first transistor being of an insulated-gate type field effect transistor.

Claim 18

A transistor circuit having a current input terminal, a first and a second current output terminal, a circuit node, a reference potential terminal and a first and a second control terminal, said circuit comprising: a first transistor having a collector-emitter current path and being coupled between said current input terminal and said reference potential terminal; a first means for having said current input terminal connected to said circuit node; a second means for having said circuit node connected to a base of said first transistor; a second transistor having a collector-emitter current path and being coupled between said first current output terminal and said reference potential terminal; a third transistor having a collector-emitter current path and being connected between said second current output terminal and said reference potential terminal; a first switching means connected between said circuit node and a base of said second transistor and to be controlled in response to a voltage level applied to said first control terminal; and a second switching means connected between said circuit node and a base of said third transistor and to be controlled in response to a voltage level applied to said second control terminal.

Claim 19

A transistor circuit having a current input terminal, a first and a second current output terminal, a circuit node, a reference potential terminal and a first and a second control terminal, said circuit comprising: a first transistor having a collector-emitter current path and being coupled between said current input terminal and said reference potential terminal; a first means for having said current input terminal connected to said circuit node; a second means for having said circuit node connected to a base of said first transistor; a second transistor having a collector-emitter current path and being coupled between said first current output terminal and said reference potential terminal; a third transistor having a collector-emitter current path and being connected between said second current output terminal and said reference potential terminal; a first switching means connected between said circuit node and a base of said second transistor and to be controlled in response to a voltage level applied to said first control terminal; and a second switching means connected between said circuit node and a base of said third transistor and to be controlled in response to a voltage level applied to said second control terminal.

Claim 20

A transistor circuit according to claim 15, wherein each of said first and said second switching means includes an insulated-gate type field effect transistor, said transistor having a source-drain path connected between said node and a base of the transistor corresponding thereto and having a gate connected to the control terminal corresponding thereto.

Claim 21

A transistor circuit according to claim 15, further comprising a source potential terminal and wherein said means for connecting said input terminal to said circuit node includes a fourth transistor of a bipolar type, said fourth transistor having a base and an emitter connected to said input terminal and said circuit node, respectively, and a collector connected to said source potential terminal, and said means for connecting said circuit node to said base of said first transistor being of an insulated-gate field effect transistor.