Patent US5063172A successfully refreshed from Google Patents.
US5063172A
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US
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Manufacture of a split-gate EPROM cell using polysilicon spacers
Assignee: National Semiconductor Corp
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Filing: 1991-02-05
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Granted: 1991-11-05
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Expires: 2011-02-05
Abstract
Abstract The present invention provides an integrated circuit fabrication method that utilizes a conductive spacer to define the gate length of the series select transistor in a split-gate memory cell. Since the length of the spacer can be controlled with great precision using existing integrated circuit process technologies, misalignment problems associated with the prior art split-gate cells are eliminated.
Inventors
- 👤 Martin H. Manley
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 12:25
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01326; H10D64/0133; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D64/031; H10D64/035
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
164 words
A method of forming a split-gate memory cell in a semiconductor substrate of a first conductivity type, the method comprising the steps of: (a) forming a conductive floating gate overlying the substrate but electrically insulated therefrom by a layer of first dielectric material, the floating gate having a layer of second dielectric material formed thereon; (b) forming a sidewall insulator on a first edge of the floating gate; (c) forming a conductive spacer adjacent to the first edge of the floating gate but insulated therefrom by the sidewall insulator; (d) forming first and second regions of a second conductivity type in the substrate using a second edge of the floating gate to define an edge of the first region, and using an edge of the conductive spacer to define an edge of the second region; (e) forming a conductive control gate in electrical contact with the conductive spacer and overlying but electrically insulated from the floating gate by the layer of second dielectric material.
Claim 2
Independent Claim
164 words
A method of forming a split-gate memory cell in a semiconductor substrate of a first conductivity type, the method comprising the steps of: (a) forming a conductive floating gate overlying the substrate but electrically insulated therefrom by a layer of first dielectric material, the floating gate having a layer of second dielectric material formed thereon; (b) forming a sidewall insulator on a first edge of the floating gate; (c) forming a conductive spacer adjacent to the first edge of the floating gate but insulated therefrom by the sidewall insulator; (d) forming first and second regions of a second conductivity type in the substrate using a second edge of the floating gate to define an edge of the first region, and using an edge of the conductive spacer to define an edge of the second region; (e) forming a conductive control gate in electrical contact with the conductive spacer and overlying but electrically insulated from the floating gate by the layer of second dielectric material.
Claim 3
Independent Claim
153 words
A method of forming a split-gate memory cell in a P- silicon substrate, the method comprising the steps of: (a) forming a polysilicon floating gate overlying the substrate but electrically insulated therefrom by a layer of gate oxide, the floating gate having a layer of ONO formed thereon; (b) forming sidewall oxide on a first edge of the floating gate; (c) forming a polysilicon spacer adjacent to the first edge of the floating gate but insulated therefrom by the sidewall oxide; (d) forming first and second N+ regions in the substrate using a second edge of the floating gate to define an edge of the first N+ region and using an edge of the polysilicon spacer to define an edge of the second N+ region; and (e) forming a conductive control gate in electrical contact with the polysilicon spacer and overlying but electrically insulated from the floating gate by the layer of ONO.
Claim 4
Independent Claim
153 words
A method of forming a split-gate memory cell in a P- silicon substrate, the method comprising the steps of: (a) forming a polysilicon floating gate overlying the substrate but electrically insulated therefrom by a layer of gate oxide, the floating gate having a layer of ONO formed thereon; (b) forming sidewall oxide on a first edge of the floating gate; (c) forming a polysilicon spacer adjacent to the first edge of the floating gate but insulated therefrom by the sidewall oxide; (d) forming first and second N+ regions in the substrate using a second edge of the floating gate to define an edge of the first N+ region and using an edge of the polysilicon spacer to define an edge of the second N+ region; and (e) forming a conductive control gate in electrical contact with the polysilicon spacer and overlying but electrically insulated from the floating gate by the layer of ONO.
Claim 5
Independent Claim
197 words
A method of forming a split-gate memory cell in a semiconductor substrate of a first conductivity type, the method comprising the steps of: (a) forming a conductive floating gate overlying the substrate but electrically insulated therefrom by a layer of first dielectric material, the floating gate having a layer of second dielectric material formed thereon; (b) forming a first region of a second conductivity type in the substrate using a first edge of the floating gate to define an edge of the first region; (c) forming first and second sidewall insulators on the first edge and a second opposing edge, respectively, of the floating gate; (d) forming first and second conductive spacers adjacent to the first and second edges, respectively, of the floating gate but insulated therefrom by the respective first and second sidewall insulators; (e) forming a second region of the second conductivity type in the substrate using an edge of the second conductive spacer to define an edge of the second region; and (f) forming a conductive control gate in electrical contact with the first and second conductive spacers and overlying but electrically insulated from the floating gate by the layer of second dielectric material.
Claim 6
Independent Claim
197 words
A method of forming a split-gate memory cell in a semiconductor substrate of a first conductivity type, the method comprising the steps of: (a) forming a conductive floating gate overlying the substrate but electrically insulated therefrom by a layer of first dielectric material, the floating gate having a layer of second dielectric material formed thereon; (b) forming a first region of a second conductivity type in the substrate using a first edge of the floating gate to define an edge of the first region; (c) forming first and second sidewall insulators on the first edge and a second opposing edge, respectively, of the floating gate; (d) forming first and second conductive spacers adjacent to the first and second edges, respectively, of the floating gate but insulated therefrom by the respective first and second sidewall insulators; (e) forming a second region of the second conductivity type in the substrate using an edge of the second conductive spacer to define an edge of the second region; and (f) forming a conductive control gate in electrical contact with the first and second conductive spacers and overlying but electrically insulated from the floating gate by the layer of second dielectric material.
Claim 7
Independent Claim
184 words
A method of forming a split-gate memory cell in a P- silicon substrate, the method comprising the steps of: (a) forming a polysilicon floating gate overlying the substrate but electrically insulated therefrom by a layer of gate oxide, the floating gate having a layer of ONO formed thereon; (b) forming a first N+ region in the substrate using a first edge of the floating gate to define an edge of the first N+ region; (c) forming first and second sidewall oxide layers on the first edge and a second opposing edge, respectively, of the floating gate; (d) forming first and second polysilicon spacers adjacent to the first and second edges, respectively, of the floating gate but insulated therefrom by the respective first and second sidewall oxide layers; (e) forming a second N+ region in the substrate using an edge of the second polysilicon spacer to define an edge of the second N+ region; and (f) forming a polysilicon control gate in electrical contact with the first and second polysilicon spacers and overlying but electrically insulated from the floating gate by the layer of ONO.
Claim 8
Independent Claim
184 words
A method of forming a split-gate memory cell in a P- silicon substrate, the method comprising the steps of: (a) forming a polysilicon floating gate overlying the substrate but electrically insulated therefrom by a layer of gate oxide, the floating gate having a layer of ONO formed thereon; (b) forming a first N+ region in the substrate using a first edge of the floating gate to define an edge of the first N+ region; (c) forming first and second sidewall oxide layers on the first edge and a second opposing edge, respectively, of the floating gate; (d) forming first and second polysilicon spacers adjacent to the first and second edges, respectively, of the floating gate but insulated therefrom by the respective first and second sidewall oxide layers; (e) forming a second N+ region in the substrate using an edge of the second polysilicon spacer to define an edge of the second N+ region; and (f) forming a polysilicon control gate in electrical contact with the first and second polysilicon spacers and overlying but electrically insulated from the floating gate by the layer of ONO.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-11-04 | 1995-05-06 | 1995-11-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-11-04 | 1999-05-06 | 1999-11-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-11-04 | 2003-05-06 | 2003-11-05 | $7700.00 | Window Closed / Lapsed |