Double diffused CMOS with Schottky to drain contacts

Claim 2

A complementary metal oxide semiconductor (CMOS) transistor pair structure comprising a p-channel transistor including a p-doped source, and ohmic contact to said p-doped source, a p-doped drain, a Schottky contact to said p-doped drain, an n-doped channel between said p-doped source and said p-doped drain, and a gate electrode overlying and insulatively spaced from said channel region, an n-channel transistor including an n-doped source, an ohmic contact to said n-doped source, an n-doped drain, a Schottky contact to said n-doped drain, a p-doped channel between said n-doped source and said n-doped drain and a gate electrode overlying and insulatively spaced from said channel region, a first voltage potential terminal connected to said ohmic contact to said p-doped source region, a second voltage potential terminal connected to said ohmic contact to said n-doped source region, an input terminal connected to said gate electrodes, and an output terminal serially connected to said drains through said Schottky contacts.

Claim 3

A double diffused complementary metal oxide semiconductor (CMOS) transistor pair structure comprising a semiconductor body having a major surface, a p-channel MOS transistor in said semiconductor body including a p-doped first device region in said semiconductor body and abutting said major surface, an n-doped region in said p-doped first device region, a p-doped source region in said n-doped region, an ohmic contact to said p-doped source region, a p-doped drain region in said p-doped first device region and spaced from said n-doped region, a Schottky contact to said p-doped drain region, and a gate electrode over and insulatively spaced from said n-doped region between said p-doped source region and said p-doped drain region, an n-channel MOS transistor in said semiconductor body including an n-doped second device region in said semiconductor body and abutting said major surface, a p-doped region in said n-doped second device region, an n-doped source region in said p-doped region, an ohmic contact to said n-doped source region, an n-doped first drain region and spaced from said p-doped region, a Schottky contact to said n-doped drain region, and a gate electrode over and insulatively spaced from said p-doped region between said n-doped source region and said n-doped drain region, means connecting a first voltage potential to said ohmic contact to said p-doped source region, means connecting a second voltage potential to said ohmic contact to said n-doped source region, means connecting an input to gate electrodes, and means serially connecting an output through said Schottky contacts to said drains.

Claim 4

A double diffused complementary metal oxide semiconductor (CMOS) transistor pair structure comprising a semiconductor body having a major surface, a p-channel MOS transistor in said semiconductor body including a p-doped first device region in said semiconductor body and abutting said major surface, an n-doped region in said p-doped first device region, a p-doped source region in said n-doped region, an ohmic contact to said p-doped source region, a p-doped drain region in said p-doped first device region and spaced from said n-doped region, a Schottky contact to said p-doped drain region, and a gate electrode over and insulatively spaced from said n-doped region between said p-doped source region and said p-doped drain region, an n-channel MOS transistor in said semiconductor body including an n-doped second device region in said semiconductor body and abutting said major surface, a p-doped region in said n-doped second device region, an n-doped source region in said p-doped region, an ohmic contact to said n-doped source region, an n-doped first drain region and spaced from said p-doped region, a Schottky contact to said n-doped drain region, and a gate electrode over and insulatively spaced from said p-doped region between said n-doped source region and said n-doped drain region, means connecting a first voltage potential to said ohmic contact to said p-doped source region, means connecting a second voltage potential to said ohmic contact to said n-doped source region, means connecting an input to gate electrodes, and means serially connecting an output through said Schottky contacts to said drains.

Claim 5

A complementary-double-diffused-metal-oxide-semiconductor transistor pair comprising: a semiconductor substrate having a top surface and a bottom surface, an insulating layer positioned on said top surface, an n-channel DMOS transistor comprising: a first well of n-type silicon semiconductor, a second well of p-type silicon contained entirely within said first well, a first pocket of n-type silicon contained entirely within said second well, a second pocket of n-type silicon contained entirely within said first well and spaced apart from said second pocket, a third pocket of p-type silicon immediately adjacent said second pocket forming a first p-n junction between said second pocket and said third pocket, positioned toward said second well but spaced apart from said second well, a first ohmic contact formed to said first pocket and to said second well electrically connecting said first pocket and said second well to a same first electrical potential, a first insulated gate electrode member formed over a region of said second well extending from an edge of said second well facing toward said third pocket to said first pocket, and a first conductive material formed over a portion of said p-n junction between said second pocket and said third pocket forming a Schottky barrier junction diode to said second pocket and an ohmic contact to said third pocket, a p-channel DMOS transistor comprising: a third well of p-type silicon semiconductor, a fourth well of n-type silicon contained entirely within said third well, a fourth pocket of p-type silicon contained entirely within said fourth well, a fifth pocket of p-type silicon contained entirely within said third well and spaced apart from said fourth pocket, a sixth pocket of n-type silicon immediately adjacent said fifth pocket forming a second p-n junction between said fifth pocket and said sixth pocket, positioned toward said fourth well but spaced apart from said fourth well, a second ohmic contact formed to said fourth pocket and to said fourth well electrically connecting said fourth pocket and said fourth well to a same second electrical potential, a second insulated gate electrode member formed over a region of said fourth well extending from an edge of said fourth well facing toward said sixth pocket to said fourth pocket, and a second conductive material formed over a portion of said second p-n junction between said fifth pocket and said sixth pocket forming a Schottky barrier junction diode to said fifth pocket and an ohmic contact to said sixth pocket and being electrically coupled to said first conductive material, and an isolating insulating region formed between said p-channel DMOS transistor and said n-channel DMOS transistor.

Claim 6

A complementary-double-diffused-metal-oxide-semiconductor transistor pair comprising: a semiconductor substrate having a top surface and a bottom surface, an insulating layer positioned on said top surface, an n-channel DMOS transistor comprising: a first well of n-type silicon semiconductor, a second well of p-type silicon contained entirely within said first well, a first pocket of n-type silicon contained entirely within said second well, a second pocket of n-type silicon contained entirely within said first well and spaced apart from said second pocket, a third pocket of p-type silicon immediately adjacent said second pocket forming a first p-n junction between said second pocket and said third pocket, positioned toward said second well but spaced apart from said second well, a first ohmic contact formed to said first pocket and to said second well electrically connecting said first pocket and said second well to a same first electrical potential, a first insulated gate electrode member formed over a region of said second well extending from an edge of said second well facing toward said third pocket to said first pocket, and a first conductive material formed over a portion of said p-n junction between said second pocket and said third pocket forming a Schottky barrier junction diode to said second pocket and an ohmic contact to said third pocket, a p-channel DMOS transistor comprising: a third well of p-type silicon semiconductor, a fourth well of n-type silicon contained entirely within said third well, a fourth pocket of p-type silicon contained entirely within said fourth well, a fifth pocket of p-type silicon contained entirely within said third well and spaced apart from said fourth pocket, a sixth pocket of n-type silicon immediately adjacent said fifth pocket forming a second p-n junction between said fifth pocket and said sixth pocket, positioned toward said fourth well but spaced apart from said fourth well, a second ohmic contact formed to said fourth pocket and to said fourth well electrically connecting said fourth pocket and said fourth well to a same second electrical potential, a second insulated gate electrode member formed over a region of said fourth well extending from an edge of said fourth well facing toward said sixth pocket to said fourth pocket, and a second conductive material formed over a portion of said second p-n junction between said fifth pocket and said sixth pocket forming a Schottky barrier junction diode to said fifth pocket and an ohmic contact to said sixth pocket and being electrically coupled to said first conductive material, and an isolating insulating region formed between said p-channel DMOS transistor and said n-channel DMOS transistor.

Claim 7

A pair of complementary-metal-oxide-semiconductor transistors comprising: a silicon semiconductor substrate having a top surface and a bottom surface, an insulating layer of silicon dioxide positioned on said top surface, an n-channel DMOS transistor comprising: a first well of n-type silicon semiconductor, a second well of p-type silicon contained entirely within said first well, a first pocket of n-type silicon contained entirely within said second well, a second pocket of n-type silicon contained entirely within said first well and spaced apart from said second pocket, a third pocket of p-type silicon immediately adjacent said second pocket forming a first p-n junction between said second pocket and said third pocket, positioned toward said second well but spaced apart from said second well, a first ohmic contact formed to said first pocket and to said second well electrically connecting said first pocket and said second well to a same first electrical potential, a first insulated gate electrode member formed over a region of said second well extending from an edge of said second well facing toward said third pocket to said first pocket, and a first conductive material formed over a portion of said p-n junction between said second pocket and said third pocket forming a Schottky barrier junction diode to said second pocket and an ohmic contact to said third pocket, a p-channel DMOS transistor comprising: a third well of p-type silicon semiconductor, a fourth well of n-type silicon contained entirely within said third well, a fourth pocket of p-type silicon contained entirely within said fourth well, a fifth pocket of p-typed silicon contained entirely within said third well and spaced apart from said fourth pocket, a sixth pocket of n-type silicon immediately adjacent said fifth pocket forming a second p-n junction between said fifth pocket and said sixth pocket, positioned toward said fourth well but spaced apart from said fourth well, a second ohmic contact formed to said fourth pocket and to said fourth well electrically connecting said fourth pocket and said fourth well to a same second electrical potential, a second insulated gate electrode member formed over a region of said fourth well extending from an edge of said fourth well facing toward said sixth pocket to said fourth pocket, and a second conductive material formed over a portion of said second p-n junction between said fifth pocket and said sixth pocket forming a Schottky barrier junction diode to said fifth pocket and an ohmic contact to said sixth pocket and being electrically coupled to said first Schottky barrier junction diode, and an isolating insulating region formed between said p-channel DMOS transistor and said n-channel DMOS transistor.

Claim 8

A pair of complementary-metal-oxide-semiconductor transistors comprising: a silicon semiconductor substrate having a top surface and a bottom surface, an insulating layer of silicon dioxide positioned on said top surface, an n-channel DMOS transistor comprising: a first well of n-type silicon semiconductor, a second well of p-type silicon contained entirely within said first well, a first pocket of n-type silicon contained entirely within said second well, a second pocket of n-type silicon contained entirely within said first well and spaced apart from said second pocket, a third pocket of p-type silicon immediately adjacent said second pocket forming a first p-n junction between said second pocket and said third pocket, positioned toward said second well but spaced apart from said second well, a first ohmic contact formed to said first pocket and to said second well electrically connecting said first pocket and said second well to a same first electrical potential, a first insulated gate electrode member formed over a region of said second well extending from an edge of said second well facing toward said third pocket to said first pocket, and a first conductive material formed over a portion of said p-n junction between said second pocket and said third pocket forming a Schottky barrier junction diode to said second pocket and an ohmic contact to said third pocket, a p-channel DMOS transistor comprising: a third well of p-type silicon semiconductor, a fourth well of n-type silicon contained entirely within said third well, a fourth pocket of p-type silicon contained entirely within said fourth well, a fifth pocket of p-typed silicon contained entirely within said third well and spaced apart from said fourth pocket, a sixth pocket of n-type silicon immediately adjacent said fifth pocket forming a second p-n junction between said fifth pocket and said sixth pocket, positioned toward said fourth well but spaced apart from said fourth well, a second ohmic contact formed to said fourth pocket and to said fourth well electrically connecting said fourth pocket and said fourth well to a same second electrical potential, a second insulated gate electrode member formed over a region of said fourth well extending from an edge of said fourth well facing toward said sixth pocket to said fourth pocket, and a second conductive material formed over a portion of said second p-n junction between said fifth pocket and said sixth pocket forming a Schottky barrier junction diode to said fifth pocket and an ohmic contact to said sixth pocket and being electrically coupled to said first Schottky barrier junction diode, and an isolating insulating region formed between said p-channel DMOS transistor and said n-channel DMOS transistor.