← Back to Patent Explorer
US5061652A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of manufacturing a semiconductor device structure employing a multi-level epitaxial structure

Assignee: International Business Machines Corp
•
Filing: 1990-01-23
•
Granted: 1991-10-29
•
Expires: 2010-01-23
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A semiconductor structure including a doped semiconductor substrate defining a surface. A buffer layer of epitaxial semiconductor material overlies the substrate surface, the buffer layer having a relatively higher dopant concentration than the substrate and being virtually free from oxygen precipitation. A layer of intrinsic semiconductor material overlies the buffer layer, and a device layer of epitaxial semiconductor material is situated on the intrinsic layer. The device layer is formed to have a relatively lower dopant concentration than the first layer. Isolation regions extend from a surface of the device layer into the buffer layer for forming an electrically isolated device region in the device layer. At least one active device is formed in the isolated device region.

Inventors

  • 👤 Robert E. Bendernagel
  • 👤 Kyong-Min Kim
  • 👤 Victor J. Silvestri
  • 👤 Pavel Smetana
  • 👤 Thomas H. Strudwick
  • 👤 William H. White

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-30 15:35
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/012; H10P; H10P14/00; H10P14/20; H10P14/24; H10P14/29; H10P14/2901; H10P14/2902; H10P14/2905; H10P14/2926; H10P14/34; H10P14/3402; H10P14/3404; H10P14/3411; H10W10/014; H10W10/10; H10W10/13; H10W10/17; H10W15/00; H10W15/01

Claims Analysis

Total Claims: 13
Claim 1
Independent Claim 207 words
A method of forming a semiconductor structure comprising the steps of: providing a doped semiconductor substrate including a surface; epitaxially growing a first layer of semiconductor material on said substrate surface, said first layer having a relatively higher dopant concentration than said substrate; epitaxially growing a second layer of semiconductor material on said first layer, said second layer having a relatively lower dopant concentration than said first layer; epitaxially growing a third layer of semiconductor material intermediate said first and second layers, said third layer having a dopant concentration lower than the dopant concentration of said second layer; and forming isolation means including a region of insulating material extending from a surface of said second layer into said first layer and terminating in said first layer for electrically isolating a device region in said second layer; said substrate having a dopant concentration in the range of 10 14 -10 19 atoms/cubic centimeter; said first layer having a thickness in the range of 0.4-20 microns and a dopant concentration in the range of 10 17 -10 20 atoms/cubic centimeter; said second layer having a dopant concentration in the range of 10 15 -10 17 atoms/cubic centimeter; and said third layer having a thickness of less than 2 microns.
Claim 2
Independent Claim 207 words
A method of forming a semiconductor structure comprising the steps of: providing a doped semiconductor substrate including a surface; epitaxially growing a first layer of semiconductor material on said substrate surface, said first layer having a relatively higher dopant concentration than said substrate; epitaxially growing a second layer of semiconductor material on said first layer, said second layer having a relatively lower dopant concentration than said first layer; epitaxially growing a third layer of semiconductor material intermediate said first and second layers, said third layer having a dopant concentration lower than the dopant concentration of said second layer; and forming isolation means including a region of insulating material extending from a surface of said second layer into said first layer and terminating in said first layer for electrically isolating a device region in said second layer; said substrate having a dopant concentration in the range of 10 14 -10 19 atoms/cubic centimeter; said first layer having a thickness in the range of 0.4-20 microns and a dopant concentration in the range of 10 17 -10 20 atoms/cubic centimeter; said second layer having a dopant concentration in the range of 10 15 -10 17 atoms/cubic centimeter; and said third layer having a thickness of less than 2 microns.
Claim 3
Dependent Claim 19 words
The method of claim 1 wherein and further including means for forming an electrical connection to said first layer.
Claim 4
Dependent Claim 21 words
The method of claim 1 and further including the step of forming at least one active device in said device region.
Claim 5
Dependent Claim 17 words
The method of claim 3 wherein said active device comprises a bipolar or an insulated gate transistor.
Claim 6
Dependent Claim 20 words
A method in accordance with claim 1 wherein said substrate has a dopant concentration of less than 10 17 atoms/cc.
Claim 7
Independent Claim 123 words
A method of forming a semiconductor structure comprising the steps of: providing a doped semiconductor substrate including a surface; epitaxially growing a first layer of semiconductor material on said substrate surface, said first layer having a dopant concentration relatively higher than the dopant concentration of said substrate; epitaxially growing a second layer of intrinsic semiconductor material on said first layer; epitaxially growing a third layer of semiconductor material on said second layer, said third layer having a dopant concentration less than the dopant concentration of said first layer; forming isolation means extending from a surface of said third layer into said first layer for forming an electrically isolated device region in said third layer; and forming an active device in said device region.
Claim 8
Independent Claim 123 words
A method of forming a semiconductor structure comprising the steps of: providing a doped semiconductor substrate including a surface; epitaxially growing a first layer of semiconductor material on said substrate surface, said first layer having a dopant concentration relatively higher than the dopant concentration of said substrate; epitaxially growing a second layer of intrinsic semiconductor material on said first layer; epitaxially growing a third layer of semiconductor material on said second layer, said third layer having a dopant concentration less than the dopant concentration of said first layer; forming isolation means extending from a surface of said third layer into said first layer for forming an electrically isolated device region in said third layer; and forming an active device in said device region.
Claim 9
Dependent Claim 17 words
The method of claim 6 wherein said active device comprises a bipolar or an insulated gate transistor.
Claim 10
Dependent Claim 100 words
The method of claim 6 wherein: said substrate has a dopant concentration in the range of 10 14 -10 19 atoms/cubic centimeter; said first layer has a thickness in the range of 0.4-20 microns and a dopant concentration in the range of 10 17 14 10 20 atoms/cubic centimeter; said second layer has a thickness of less than 2 microns and a dopant concentration less than the dopant concentration of said third layer; and said third layer has a thickness in the range of 0.4-10 microns and a dopant concentration in the range of 10 15 -10 17 atoms/cubic centimeter.
Claim 11
Dependent Claim 20 words
A method in accordance with claim 6 wherein said substrate has a dopant concentration of less than 10 17 atoms/cc.
Claim 12
Dependent Claim 15 words
The method of claim 6 wherein said substrate and epitaxial semiconductor material each includes silicon.
Claim 13
Dependent Claim 16 words
The method of claim 10 wherein said first layer is doped with Group IV impurity atoms.

References Cited (Backward Citations)

US3772097A Cited
US3607465A Cited
US3775196A Cited
US3547716A Cited
US3769105A Cited
US3929526A Cited
US3912555A Cited
US4168997A Cited
EP0224717A2 Cited
US4936928A Cited
JPH0199254A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1994-10-28 1995-04-29 1995-10-29 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1998-10-28 1999-04-29 1999-10-29 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2002-10-28 2003-04-29 2003-10-29 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag