Method of fabricating a thin-film transistor

Claim 1

A method of fabricating a thin-film transistor comprising: a first step of forming a transparent conductive film on a substrate; a second step of patterning said transparent conductive film by etching to form a source electrode and a drain electrode in a spaced-apart relation to each other; a third step of forming an element-containing layer by diffusing into the surface of said source and drain electrodes a Group V element such as phosphorus, arsenic, antimony or bismuth or a Group III element such as boron, aluminum or gallium; a fourth step of forming a semiconductor layer between and on portions of said source and drain electrodes, thereby simultaneously forming first and second ohmic contact layers between said semiconductor layer and said source and drain electrodes; a fifth step of forming a semiconductor layer between and on portions of said source and drain electrodes, thereby simultaneously forming first and second ohmic contact layers between said semiconductor layer and said source and drain electrodes; a fifth step of forming a gate insulating film on said semiconductor layer; and a sixth step of forming a gate electrode on said gate insulating film.

Claim 2

A method of fabricating a thin-film transistor comprising: a first step of forming a transparent conductive film on a substrate; a second step of patterning said transparent conductive film by etching to form a source electrode and a drain electrode in a spaced-apart relation to each other; a third step of forming an element-containing layer by diffusing into the surface of said source and drain electrodes a Group V element such as phosphorus, arsenic, antimony or bismuth or a Group III element such as boron, aluminum or gallium; a fourth step of forming a semiconductor layer between and on portions of said source and drain electrodes, thereby simultaneously forming first and second ohmic contact layers between said semiconductor layer and said source and drain electrodes; a fifth step of forming a semiconductor layer between and on portions of said source and drain electrodes, thereby simultaneously forming first and second ohmic contact layers between said semiconductor layer and said source and drain electrodes; a fifth step of forming a gate insulating film on said semiconductor layer; and a sixth step of forming a gate electrode on said gate insulating film.

Claim 4

The method of fabricating a thin-film transistor according to one of claims 1 and 2, wherein in said third step said element-containing layer is formed through plasma assisted chemical vapor deposition by supplying a gas containing said Group V or III element to said substrate held at an elevated temperature and also supplying RF power.

Claim 6

The method of fabricating a thin-film transistor according to one of claims 1 and 2, wherein in said third step Group V or III element is thermally diffused in said source and drain electrodes.

Claim 7

A method of fabricating a thin-film transistor comprising: a first step of forming a transparent conductive film on a substrate; a second step of patterning said transparent conductive film by isotropic etching to form a source electrode and a drain electrode having tapered side surfaces in a spaced-apart relation to each other; a third step of forming first and second ohmic contact layers on the entirety of said tapered side surfaces of said source and drain electrodes by diffusing a Group III or a Group V element into said tapered side surfaces; a fourth step of forming a semiconductor layer over said first and second ohmic contact layers on said substrate; a fifth step of forming a gate insulating film on said semiconductor layer; and a sixth step of forming a gate electrode on said gate insulating film.

Claim 8

A method of fabricating a thin-film transistor comprising: a first step of forming a transparent conductive film on a substrate; a second step of patterning said transparent conductive film by isotropic etching to form a source electrode and a drain electrode having tapered side surfaces in a spaced-apart relation to each other; a third step of forming first and second ohmic contact layers on the entirety of said tapered side surfaces of said source and drain electrodes by diffusing a Group III or a Group V element into said tapered side surfaces; a fourth step of forming a semiconductor layer over said first and second ohmic contact layers on said substrate; a fifth step of forming a gate insulating film on said semiconductor layer; and a sixth step of forming a gate electrode on said gate insulating film.