Patent US5059829A successfully refreshed from Google Patents.
US5059829A
Expired / Lapsed
US
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Logic level shifting circuit with minimal delay
Assignee: Motorola Solutions Inc
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Filing: 1990-09-04
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Granted: 1991-10-22
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Expires: 2010-09-04
Abstract
Abstract A circuit enabling the conversion of a set of ECL and a set of CMOS logic levels has a differential amplifier, two emitter followers, a current switching circuit, and a level shifting circuit. The differential amplifier provides a common mode input to two emitter followers which switch very rapidly using ECL voltage levels. High operational speed is accomplished by providing a relaxation current during logic high-to-low voltage transients. The current switching circuit conserves power consumption by switching off the relaxation current during logic low-to-high transients, during which time the emitter followers switch sufficiently fast. The level shifting circuit converts the set of ECL logic voltage levels to a set of CMOS voltage levels and the CMOS output voltage is used to control the current switching circuit without introducing a switching delay time.
Inventors
- 👤 Stephen T. Flannagan
- 👤 Tai-Sheng Feng
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 16:22
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0008; H03K19/0016; H03K19/01; H03K19/013; H03K19/0136; H03K19/0175; H03K19/017509; H03K19/017518; H03K19/017527
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
234 words
A logic level shifting circuit with minimal delay comprising: a first current source; current steering means coupled to the first current source and having differential mode inputs for respectively receiving differential mode input voltages associated with a first set of logic levels and having a first pair of differential outputs, each providing a current proportional to the differential mode input voltages; a first pair of passive loads respectively coupled to the first pair of differential outputs of the current steering means, for providing a first pair of voltages in response to the currents, each voltage of the first pair of voltages provided in response to a predetermined one of the currents from the current steering means; a pair of voltage followers respectively coupled to the first pair of voltages for respectively providing at a second pair of voltages associated with the first set of logic levels; a pair of switched current control means respectively coupled to a second pair of voltages of the pair of voltage followers; a second current source coupled to the pair of switched current control means for providing a predetermined current to the pair of switched current control means; and buffer means coupled to one of the second pair of voltages and providing a third pair of output voltages associated with a second set of logic levels and coupled to control electrodes of the pair of switched current control means.
Claim 2
Dependent Claim
234 words
A logic level shifting circuit with minimal delay comprising: a first current source; current steering means coupled to the first current source and having differential mode inputs for respectively receiving differential mode input voltages associated with a first set of logic levels and having a first pair of differential outputs, each providing a current proportional to the differential mode input voltages; a first pair of passive loads respectively coupled to the first pair of differential outputs of the current steering means, for providing a first pair of voltages in response to the currents, each voltage of the first pair of voltages provided in response to a predetermined one of the currents from the current steering means; a pair of voltage followers respectively coupled to the first pair of voltages for respectively providing at a second pair of voltages associated with the first set of logic levels; a pair of switched current control means respectively coupled to a second pair of voltages of the pair of voltage followers; a second current source coupled to the pair of switched current control means for providing a predetermined current to the pair of switched current control means; and buffer means coupled to one of the second pair of voltages and providing a third pair of output voltages associated with a second set of logic levels and coupled to control electrodes of the pair of switched current control means.
Claim 3
Dependent Claim
19 words
The level shifting circuit of claim 1 wherein the pair of voltage followers comprise a pair of emitter followers.
Claim 4
Dependent Claim
19 words
The level shifting circuit of claim 1 wherein the pair of voltage followers comprise a pair of source followers.
Claim 5
Dependent Claim
19 words
The level shifting circuit of claim 1 wherein the current steering means comprise an emitter coupled pair of transistors.
Claim 6
Dependent Claim
27 words
The level shifting circuit of claim 1 wherein at least one of the first and second current sources selectively provides current in response to a control signal.
Claim 7
Dependent Claim
43 words
The level shifting circuit of claim 1 wherein the pair of switched current control means comprises a first field effect transistor coupled in parallel with a third current source and a second field effect transistor coupled in parallel with a fourth current source.
Claim 8
Dependent Claim
25 words
The level shifting circuit of claim 1 wherein the second set of logic levels has a greater excursion than the first set of logic levels.
Claim 9
Dependent Claim
16 words
The level shifting circuit of claim 1 wherein the current steering means comprises a differential amplifier.
Claim 10
Dependent Claim
456 words
A logic level shifting circuit with minimal delay for providing first and second output voltages respectively having a first set of logic levels in response to receiving first and second input voltages respectively having a second set of logic levels, comprising: a differential amplifier having first and second inputs for receiving first and second input voltages respectively having first and second logic levels associated with a first set of logic levels, and having first and second output terminals and a third output terminal; a first current source having a first terminal coupled to the third output terminal, and a second terminal coupled to a first reference voltage terminal; a first resistor having a first terminal coupled to the first output terminal of the differential amplifier, and a second terminal coupled to a second reference voltage terminal; a second resistor having a first terminal coupled to the second output terminal of the differential amplifier, and a second terminal coupled to the second reference voltage terminal; a first transistor of a first processing type having a first current electrode coupled to the second reference voltage terminal, a control electrode coupled to the first output terminal of the differential amplifier, and a second current electrode; a second transistor of the first processing type having a first current electrode coupled to the second reference voltage terminal, a control electrode coupled to the second output terminal of the differential amplifier, and a second current electrode; a third transistor of a second processing type having a first current electrode coupled to the second current electrode of the first transistor, a control electrode, and a second current electrode; a fourth transistor of the second processing type having a first current electrode coupled to the second current electrode of the second transistor, a control electrode, and a second current electrode; a second current source having a first terminal coupled to the second current electrodes of the third and fourth transistors, and a second terminal coupled to the first reference voltage terminal; a third current source having a first terminal coupled to the first current electrode of the third transistor, and a second terminal coupled to the first reference voltage terminal; a fourth current source having a first terminal coupled to the first current electrode of the fourth transistor, and a second terminal coupled to the first reference voltage terminal; and buffer means having an input coupled to the second current electrode of the second transistor, a first output coupled to the control electrode of the third transistor, and a second output coupled to the control electrode of the fourth transistor, said buffer means providing a pair of output voltages respectively having first and second logic levels associated with a second set of logic levels.
Claim 11
Dependent Claim
456 words
A logic level shifting circuit with minimal delay for providing first and second output voltages respectively having a first set of logic levels in response to receiving first and second input voltages respectively having a second set of logic levels, comprising: a differential amplifier having first and second inputs for receiving first and second input voltages respectively having first and second logic levels associated with a first set of logic levels, and having first and second output terminals and a third output terminal; a first current source having a first terminal coupled to the third output terminal, and a second terminal coupled to a first reference voltage terminal; a first resistor having a first terminal coupled to the first output terminal of the differential amplifier, and a second terminal coupled to a second reference voltage terminal; a second resistor having a first terminal coupled to the second output terminal of the differential amplifier, and a second terminal coupled to the second reference voltage terminal; a first transistor of a first processing type having a first current electrode coupled to the second reference voltage terminal, a control electrode coupled to the first output terminal of the differential amplifier, and a second current electrode; a second transistor of the first processing type having a first current electrode coupled to the second reference voltage terminal, a control electrode coupled to the second output terminal of the differential amplifier, and a second current electrode; a third transistor of a second processing type having a first current electrode coupled to the second current electrode of the first transistor, a control electrode, and a second current electrode; a fourth transistor of the second processing type having a first current electrode coupled to the second current electrode of the second transistor, a control electrode, and a second current electrode; a second current source having a first terminal coupled to the second current electrodes of the third and fourth transistors, and a second terminal coupled to the first reference voltage terminal; a third current source having a first terminal coupled to the first current electrode of the third transistor, and a second terminal coupled to the first reference voltage terminal; a fourth current source having a first terminal coupled to the first current electrode of the fourth transistor, and a second terminal coupled to the first reference voltage terminal; and buffer means having an input coupled to the second current electrode of the second transistor, a first output coupled to the control electrode of the third transistor, and a second output coupled to the control electrode of the fourth transistor, said buffer means providing a pair of output voltages respectively having first and second logic levels associated with a second set of logic levels.
Claim 12
Dependent Claim
21 words
The logic level shifting circuit of claim 9 wherein the first and second transistors of first processing type are bipolar transistors.
Claim 13
Dependent Claim
21 words
The logic level shifting circuit of claim 10 wherein the third and fourth transistors of second processing type are MOS transistors.
Claim 14
Dependent Claim
30 words
The logic level shifting circuit of claim 9 wherein the first set of logic levels are ECL logic levels and the second set of logic levels are MOS logic levels.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-10-21 | 1995-04-22 | 1995-10-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-10-21 | 1999-04-22 | 1999-10-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-10-21 | 2003-04-22 | 2003-10-22 | $7700.00 | Window Closed / Lapsed |