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US5059825A
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Nand gate circuit
Assignee: Fujitsu Ltd
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Filing: 1989-10-19
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Granted: 1991-10-22
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Expires: 2009-10-19
Abstract
Abstract A NAND gate circuit which can be used for a decoder circuit, includes a high potential voltage source (V cc ), an output terminal (V OUT ), and a load element (T 1 ) connected between the high potential electric voltage source (V cc ) and the output terminal (V OUT ). A driving circuit is serially connected with the output terminal (V OUT ), and a low potential voltage source (V ss ), and has a plurality of driving transistors (T 2 , T 3 ) which are serially arranged. An input signal is applied to each gate. At least one transistor, constituting the driving circuit, has a driving performance different from the other transistors of the driving circuit. An ideal NAND gate circuit can be provided in which erroneous operation due to noise can be effectively prevented by setting the input threshold voltage to a constant voltage no matter what the combination of the input signals.
Inventors
- 👤 Masanobu Yoshida
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 21:55
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/20; H03K19/003; H03K19/00346; H03K19/00361; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/09441; H03K19/09443
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
97 words
A NAND gate circuit comprising: a high potential voltage source line; an output terminal; a low potential voltage source line; a load element connected between said high potential voltage source line and said output terminal; and a driving circuit, connected between said output terminal and said low potential voltage source line, including a plurality of driving transistors connected in series, said driving transistors being controlled by an input signal being applied to each gate, at least one of the driving transistors having a driving performance different from that of the other driving transistors constituting said driving circuit.
Claim 2
Dependent Claim
97 words
A NAND gate circuit comprising: a high potential voltage source line; an output terminal; a low potential voltage source line; a load element connected between said high potential voltage source line and said output terminal; and a driving circuit, connected between said output terminal and said low potential voltage source line, including a plurality of driving transistors connected in series, said driving transistors being controlled by an input signal being applied to each gate, at least one of the driving transistors having a driving performance different from that of the other driving transistors constituting said driving circuit.
Claim 3
Dependent Claim
36 words
A NAND gate circuit according to claim 1, wherein said driving transistors are comprised of a first transistor connected closest to said output terminal, the first transistor having the highest driving performance of said driving transistors.
Claim 4
Dependent Claim
39 words
A NAND gate circuit according to claim 1, wherein said driving transistors are comprised of a first transistor and a second transistor, said first transistor, connected closest to said output terminal, having driving performance higher than said second transistor.
Claim 5
Dependent Claim
21 words
A NAND gate circuit according to claim 1, wherein all the driving transistors constituting said driving circuit, have different driving performances.
Claim 6
Dependent Claim
23 words
A NAND gate circuit according to claim 1, wherein the driving transistors, connected closer to the output terminal have a higher driving performance.
Claim 7
Dependent Claim
131 words
A NAND gate circuit comprising: a high potential voltage source line; an output terminal; a low potential voltage source line; a load element connected between said high potential voltage source line and said output terminal; and a driving circuit, connected between said output terminal and said low potential voltage source line, including a plurality of driving transistors connected in series, said driving transistors being controlled by an input signal being applied to each gate, at least one of the driving transistors having a driving performance different from that of the other driving transistors constituting said driving circuit, said driving transistors are classified into a plurality of groups, each of the transistors belonging to a group having the same driving performance, which is different from that of those belonging to other groups.
Claim 8
Dependent Claim
131 words
A NAND gate circuit comprising: a high potential voltage source line; an output terminal; a low potential voltage source line; a load element connected between said high potential voltage source line and said output terminal; and a driving circuit, connected between said output terminal and said low potential voltage source line, including a plurality of driving transistors connected in series, said driving transistors being controlled by an input signal being applied to each gate, at least one of the driving transistors having a driving performance different from that of the other driving transistors constituting said driving circuit, said driving transistors are classified into a plurality of groups, each of the transistors belonging to a group having the same driving performance, which is different from that of those belonging to other groups.
Claim 9
Dependent Claim
149 words
A NAND gate circuit comprising: a high potential voltage source line; an output terminal; a low potential voltage source line; a load element connected between said high potential voltage source line and said output terminal; and a driving circuit, connected between said output terminal and said low potential voltage source line, including a plurality of driving transistors connected in series, said driving transistors being controlled by an input signal being applied to each gate, at least one of the driving transistors having a driving performance different from that of the other driving transistors constituting said driving circuit, said driving transistors are classified into a plurality of groups, each of the transistors belonging to a group having the same driving performance, which is different from that of those belonging to other groups, the group of transistors, connected closer to said low potential voltage source line, having a lower driving performance.
Claim 10
Dependent Claim
149 words
A NAND gate circuit comprising: a high potential voltage source line; an output terminal; a low potential voltage source line; a load element connected between said high potential voltage source line and said output terminal; and a driving circuit, connected between said output terminal and said low potential voltage source line, including a plurality of driving transistors connected in series, said driving transistors being controlled by an input signal being applied to each gate, at least one of the driving transistors having a driving performance different from that of the other driving transistors constituting said driving circuit, said driving transistors are classified into a plurality of groups, each of the transistors belonging to a group having the same driving performance, which is different from that of those belonging to other groups, the group of transistors, connected closer to said low potential voltage source line, having a lower driving performance.
Claim 11
Dependent Claim
24 words
A NAND gate circuit according to claim 1, wherein said NAND gate circuit is used for a decoder circuit of a semiconductor memory device.
Claim 12
Dependent Claim
21 words
A NAND gate circuit according to claim 1, wherein said driving performance is determined by the channel width and channel length.
Claim 13
Dependent Claim
27 words
A NAND gate circuit according to claim 1, wherein said driving performance is determined by the concentration of impurities in a channel region of said driving transistor.
Claim 14
Dependent Claim
26 words
A NAND gate circuit according to claim 1, wherein said driving performance is determined by the thickness of a gate oxide film of said driving transistor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-10-21 | 1995-04-22 | 1995-10-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-10-21 | 1999-04-22 | 1999-10-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-10-21 | 2003-04-22 | 2003-10-22 | $7700.00 | Window Closed / Lapsed |