Patent US5058112A successfully refreshed from Google Patents.
US5058112A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Programmable fault insertion circuit
Assignee: AG Communication Systems Corp
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Filing: 1989-07-31
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Granted: 1991-10-15
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Expires: 2009-07-31
Abstract
Abstract A fault insertion circuit is disclosed which generates and applies a fault signal to a digital circuit under test. The fault insertion circuit includes fault insertion hardware connected to the digital circuit under test. The fault insertion hardware is arranged to select, generate and apply the fault signal. A programmable controller and communication circuit are also included. The communication circuit is connected to the controller and to a data terminal, personal computer or any other source of programming commands and instructions. The communication circuit receives the programming commands and instructions from the data terminal and transmits the commands and instructions to the controller. The controller in response to the received commands and instructions transmits control signals to the fault insertion hardware, thereby, generating and applying a fault signal to the digital circuit under test.
Inventors
- 👤 Walter J. Namitz
- 👤 Charles S. Chang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 14:27
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/2205; G06F11/2215; G06F11/26; G06F11/261
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
561 words
A fault insertion circuit arranged to generate and apply a fault signal to a digital circuit under test, said digital circuit under test including an input connector having a plurality of input pins, said fault insertion circuit comprising; fault insertion hardware connected to said digital circuit under test, said fault insertion hardware including at least one output connector having a plurality of output pins, said fault insertion hardware output connector connected to said digital circuit under test input connector with each pin of said output connector pin mated to respective pin of said input connector, said fault insertion hardware further including a plurality of fault signal generating circuits, each fault signal generating circuit connected to a respective output connector pin, and selection logic circuits for selecting and enabling a respective one of said plurality of fault signal generating circuits; a microcomputer circuit connected to said selection logic circuits, said microcomputer circuit under direction of an operating program is arranged to control said selection logic circuits; a communication circuit connected to said microcomputer circuit and to a source of commands and instructions, said communication circuit arranged to receive commands and instructions from said source of commands and instructions and to transmit said commands and instruction to said microcomputer circuit, and said microcomputer circuit in response to said received commands and instructions and under direction of said operating program interprets said commands and instructions and transmits control signals to said selection logic circuits, enabling a respective one of said plurality of fault signal generating circuits and applying the fault signal generated therefrom to said digital circuit under test; said microcomputer circuit, under direction of said operating program transmits to said selection logic circuits control signals disabling said enabled signal generating circuit, and responsive to the disabling of the enabled signal generating circuit said microcomputer transmits a completion signal to said communication circuit, whereby, said completion signal is transmitted to said source of commands and instructions; said microcomputer circuit comprising a microcomputer; maintenance control means connected between said microcomputer and said selection logic circuits; data transfer storage means connected between said microcomputer and said selection logic circuits; and data return storage means connected to said microcomputer and further connected to said data transfer storage means; said microcomputer being operated to provide a maintenance enable signal and a maintenance disable signal, and further operated to provide data signals for control of said selection logic circuits; said maintenance control means being operated in response to said maintenance enable signal to provide a selection logic disable signal, and further operated in response to said maintenance disable signal to provide a selection logic enable signal; said data transfer storage means being operated to store said data signals and provide stored data signals; said selection logic circuits being operated in response to said selection logic enable signal and a particular arrangement of said stored data signals to select and enable said respective one of said plurality of fault signal generating circuits; said selection logic circuits being further operated in response to said selection logic disable signal to inhibit said selection and enabling of said fault signal generating circuits; said data return storage means being operated to store said stored data signals and to provide data return storage signals; and said microcomputer being further operated to retrieve said data return storage signals and to compare them with said data signals.
Claim 2
Dependent Claim
561 words
A fault insertion circuit arranged to generate and apply a fault signal to a digital circuit under test, said digital circuit under test including an input connector having a plurality of input pins, said fault insertion circuit comprising; fault insertion hardware connected to said digital circuit under test, said fault insertion hardware including at least one output connector having a plurality of output pins, said fault insertion hardware output connector connected to said digital circuit under test input connector with each pin of said output connector pin mated to respective pin of said input connector, said fault insertion hardware further including a plurality of fault signal generating circuits, each fault signal generating circuit connected to a respective output connector pin, and selection logic circuits for selecting and enabling a respective one of said plurality of fault signal generating circuits; a microcomputer circuit connected to said selection logic circuits, said microcomputer circuit under direction of an operating program is arranged to control said selection logic circuits; a communication circuit connected to said microcomputer circuit and to a source of commands and instructions, said communication circuit arranged to receive commands and instructions from said source of commands and instructions and to transmit said commands and instruction to said microcomputer circuit, and said microcomputer circuit in response to said received commands and instructions and under direction of said operating program interprets said commands and instructions and transmits control signals to said selection logic circuits, enabling a respective one of said plurality of fault signal generating circuits and applying the fault signal generated therefrom to said digital circuit under test; said microcomputer circuit, under direction of said operating program transmits to said selection logic circuits control signals disabling said enabled signal generating circuit, and responsive to the disabling of the enabled signal generating circuit said microcomputer transmits a completion signal to said communication circuit, whereby, said completion signal is transmitted to said source of commands and instructions; said microcomputer circuit comprising a microcomputer; maintenance control means connected between said microcomputer and said selection logic circuits; data transfer storage means connected between said microcomputer and said selection logic circuits; and data return storage means connected to said microcomputer and further connected to said data transfer storage means; said microcomputer being operated to provide a maintenance enable signal and a maintenance disable signal, and further operated to provide data signals for control of said selection logic circuits; said maintenance control means being operated in response to said maintenance enable signal to provide a selection logic disable signal, and further operated in response to said maintenance disable signal to provide a selection logic enable signal; said data transfer storage means being operated to store said data signals and provide stored data signals; said selection logic circuits being operated in response to said selection logic enable signal and a particular arrangement of said stored data signals to select and enable said respective one of said plurality of fault signal generating circuits; said selection logic circuits being further operated in response to said selection logic disable signal to inhibit said selection and enabling of said fault signal generating circuits; said data return storage means being operated to store said stored data signals and to provide data return storage signals; and said microcomputer being further operated to retrieve said data return storage signals and to compare them with said data signals.
Claim 3
Dependent Claim
17 words
A fault insertion circuit as claimed in claim 1, wherein said maintenance control means comprises a flip-flop.
Claim 4
Dependent Claim
243 words
A fault insertion circuit as claimed in claim 1, wherein a first group of said fault signal generating circuits is operative to provide fault signals of a first characteristic, and a second group of said fault signal generating circuits is operative to provide fault signals of a second characteristic; said maintenance control means comprising: a D-type flip-flop having its clock and clear inputs connected to said microcomputer; and first and second gating means, each having a first input connected to the Q output of said D-type flip-flop and a second input connected to said microcomputer; said selection logic circuits comprising a first selection logic circuit connected to the output of said first gating means, and a second selection logic circuit connected to the output of said second gating means; said first selection logic circuit being operated in response to said selection logic enable signal and each particular arrangement of a first group of said stored data signals to select and enable a respective one of a first group of said plurality of said fault signal generating circuits which provide said fault signals of a first characteristic; and said second selection logic circuit being operated in response to said selection logic enable signal and each particular arrangement of a second group of said stored data signals to select and enable a respective one of a second group of said plurality of said fault generating circuits which provide said fault signals of a second characteristic.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-10-14 | 1995-04-15 | 1995-10-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-10-14 | 1999-04-15 | 1999-10-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-10-14 | 2003-04-15 | 2003-10-15 | $7700.00 | Window Closed / Lapsed |