CMOS RAM having a complementary channel sense amplifier

Claim 1

A semiconductor memory comprising: a plurality of bit line pairs each comprising first and second complementary bit lines for transferring data; a plurality of word lines extending across said plurality of bit line pairs; a plurality of memory cells located at intersections of said bit line pairs and said word lines and coupled thereto for storing data; a plurality of first field effect transistors ("FETs"), each having a control electrode to which a gate signal is applied and a source-drain path which interconnects a first node to said first bit line of a respective one of said plurality of bit line pairs, the control electrodes of said first FETs being interconnected in common with each other; a plurality of second FETs, each having a control electrode to which the gate signal is applied, the control electrodes of said second FETs being interconnected in common with each other and to the control electrodes of said first FETs, each of said second FET's having a source-drain path which interconnects a second node to said second bit line of a respective one of said plurality of bit line pairs; a plurality of sense amplifier circuits each connected across the first and second nodes associated with a respective one of said plurality of bit line pairs for sensing potentials on the first and second nodes and amplifying the sensed potentials thereon, each of said sense amplifier circuit comprising a first and a second sense amplifier of opposite polarity; and a plurality of transfer gate means, each connected between a corresponding one of the first and second nodes of a respective sense amplifier circuit and a data bus and operative in response to a signal associated with an address designating one of said plurality of bit line pairs for transferring the amplified potentials on the first and second nodes to the data bus; said plurality of first and second FETs being complementarily controlled in response to a predetermined potential of the gate signal to connect said first and second bit lines to the first and second nodes, respectively, said predetermined potential being selected between a threshold voltage of said plurality of first and second FETs and a voltage equal to the threshold voltage plus a reference voltage at which said first and second bit lines are precharged prior to application of the gate signal to the control electrodes.